{
  "abstract": "We present a fault-tolerant quantum-memory architecture that concatenates four distance-t rotated surface-code patches with the [[4,2,2]] outer code, encoding two logical qubits at code distance d = 2t in a physical footprint of N < 2(2t+1)^2 qubits on a square lattice with nearest-neighbor connectivity. The outer-code stabilizer generators XXXX and ZZZZ, each of physical weight 4t, are measured in situ via verified Greenberger-Horne-Zeilinger (GHZ) ancillae distributed through narrow corridors between adjacent patches, without lattice surgery or long-range gates. The outer-code gadgets introduce hyperedge fault mechanisms, but by design each decomposes into graphlike components, so the complete syndrome is decoded by a single minimum-weight-perfect-matching pass. Circuit-level simulations show logical error rates that scale as p^t, consistent with distance-2t protection. Finally, we implement the construction experimentally on a 105-qubit Willow superconducting processor in both the ZZ and XX memory bases. With the correlated-matching decoder, increasing the code distance from d = 4 to d = 6 reduces the block logical error rate by a factor of 1.52. The construction thus provides a near-term testbed for concatenated architectures beyond the standard surface code.",
  "abstract_shown": true,
  "affiliations": [],
  "article_type": null,
  "arxiv": "2610.21357",
  "author_total": 8,
  "authors": [
    {
      "name": "Mohamed A. Shalby"
    },
    {
      "name": "Alexandre Bourassa"
    },
    {
      "name": "Amir Karamlou"
    },
    {
      "name": "Leigh Martin"
    },
    {
      "name": "Alexis Morvan"
    },
    {
      "name": "Nicholas Noll"
    },
    {
      "name": "Craig Gidney"
    },
    {
      "name": "Leonid P. Pryadko"
    }
  ],
  "bibtex": "https://research.draconitic.com/paper/0n81jzda2wj3f.bib",
  "cited_by": 0,
  "doi": "10.48550/arxiv.2610.21357",
  "fulltext_url": null,
  "id": "0n81jzda2wj3f",
  "issns": [],
  "landing_url": "https://arxiv.org/abs/2610.21357",
  "language": null,
  "licence": "LicenseRef-arXiv-nonexclusive-1.0",
  "licence_label": "arXiv licence",
  "licence_source": "article",
  "licence_url": "http://arxiv.org/licenses/nonexclusive-distrib/1.0/",
  "metadata_licence": "CC0-1.0",
  "native_subjects": [
    [
      "arxiv",
      "quant-ph"
    ],
    [
      "openalex",
      "1702|Quantum Computing Algorithms and Architecture"
    ]
  ],
  "openalex": "W7222648965",
  "pdf_url": "https://arxiv.org/pdf/2610.21357",
  "pmcid": null,
  "pmid": null,
  "published": "2026-10-15",
  "publisher": null,
  "ris": "https://research.draconitic.com/paper/0n81jzda2wj3f.ris",
  "sources": [
    {
      "first_seen": "2026-10-30T12:29:50Z",
      "native_id": "2610.21357",
      "source": "arxiv",
      "url": "https://arxiv.org/abs/2610.21357"
    }
  ],
  "subjects": [
    {
      "field": "physics",
      "origin": "arxiv:quant-ph",
      "subfield": "quantum"
    }
  ],
  "title": "Stitched surface codes: planar concatenation through GHZ corridors",
  "title_text": "Stitched surface codes: planar concatenation through GHZ corridors",
  "type": "preprint",
  "updated_at": "2026-10-30T12:29:50Z",
  "url": "https://research.draconitic.com/paper/0n81jzda2wj3f",
  "venue": "arXiv",
  "versions": []
}