{
  "abstract": "We present an automated method for reducing fault-tolerant circuits through fault-equivalent rewrites. Starting from a known fault-tolerant circuit, the search applies non-reducing enabling rules to expose Bell-pair reductions, each of which removes an ancilla preparation and a CNOT gate. Because every search transition preserves fault equivalence, the resulting circuits inherit the fault-tolerance properties of the input circuit. Candidate circuits are evaluated using circuit-level Monte Carlo simulation. For Shor-style syndrome extraction with the $[[7,1,3]]$ code, our method reduces one syndrome-measurement round from 30 to 18 ancilla preparations and from 54 to 42 CNOT gates. At a physical two-qubit error rate of $p = 10^{-3}$, the optimized circuit lowers the logical error rate by approximately 21% for both logical basis states. The reduction ranges from 13% to 23% over a range of $p$ spanning two orders of magnitude. We also apply the method to Steane-based dynamic syndrome extraction constructed from Goto's verified logical-$\\lvert 0 \\rangle$ preparation, in which the verification qubit serves as a flag. The search selects a circuit using four ancillas and 14 CNOT gates, matching the resource counts of the previous design but with an improved CNOT depth. Under depolarizing idle noise at $3p/10$ the selected circuit lowers the logical error rate by approximately 15% for both logical basis states, and by approximately 10% at $p/10$. These results demonstrate that automated fault-equivalent rewriting can identify circuits with lower resource costs or improved logical performance without separately verifying the fault tolerance of every candidate.",
  "abstract_shown": true,
  "affiliations": [],
  "article_type": null,
  "arxiv": "2610.09749",
  "author_total": 3,
  "authors": [
    {
      "name": "Hyeongjun Jeon"
    },
    {
      "name": "Jeonghoon Lee"
    },
    {
      "name": "Taehyun Kim"
    }
  ],
  "bibtex": "https://research.draconitic.com/paper/2vpy2b1z4wr6h.bib",
  "cited_by": 0,
  "doi": "10.48550/arxiv.2610.09749",
  "fulltext_url": null,
  "id": "2vpy2b1z4wr6h",
  "issns": [],
  "landing_url": "https://arxiv.org/abs/2610.09749",
  "language": null,
  "licence": "CC-BY-4.0",
  "licence_label": "CC BY 4.0",
  "licence_source": "article",
  "licence_url": "http://creativecommons.org/licenses/by/4.0/",
  "metadata_licence": "CC0-1.0",
  "native_subjects": [
    [
      "arxiv",
      "quant-ph"
    ],
    [
      "openalex",
      "1702|Quantum Computing Algorithms and Architecture"
    ]
  ],
  "openalex": "W7220910384",
  "pdf_url": "https://arxiv.org/pdf/2610.09749",
  "pmcid": null,
  "pmid": null,
  "published": "2026-10-13",
  "publisher": null,
  "ris": "https://research.draconitic.com/paper/2vpy2b1z4wr6h.ris",
  "sources": [
    {
      "first_seen": "2026-10-30T12:29:11Z",
      "native_id": "2610.09749",
      "source": "arxiv",
      "url": "https://arxiv.org/abs/2610.09749"
    }
  ],
  "subjects": [
    {
      "field": "physics",
      "origin": "arxiv:quant-ph",
      "subfield": "quantum"
    }
  ],
  "title": "Automated reduction of fault-tolerant circuits",
  "title_text": "Automated reduction of fault-tolerant circuits",
  "type": "preprint",
  "updated_at": "2026-10-30T12:29:11Z",
  "url": "https://research.draconitic.com/paper/2vpy2b1z4wr6h",
  "venue": "arXiv",
  "versions": []
}