{
  "abstract": "Multiplexers (MUXs) and demultiplexers (DEMUXs) are essential data-routing circuits used in memory addressing, processor datapaths, communication interfaces, and reconfigurable systems. However, CMOS scaling increases leakage power, while conventional MTCMOS techniques introduce delay, series-resistance, and control overhead. This work proposes a topology-aware high-threshold-voltage (HVT) MTCMOS power-gating architecture for cascaded transmission-gate (TG) based 4:1 MUX and 1:4 DEMUX circuits in 90 nm CMOS. The architecture uses a select-controlled HVT PMOS header at a topology-dependent TG stage and a block-level HVT header, requiring only two additional transistors without a dedicated sleep network. The MUX reduces power by 40.0% with a 16.0% delay penalty and improves PDP by 30.4%. The DEMUX reduces power by 28.6% and delay by 57.2%, achieving 69.4% lower PDP and 86.9% lower EDP. RC-delay analysis explains the topology-dependent behavior and establishes a scalable stage-selection principle. Cadence Virtuoso simulations, PVT analysis, Monte Carlo analysis, and DC sweeps confirm circuit robustness and functional integrity.",
  "abstract_shown": true,
  "affiliations": [
    "Department of Electrical, Electronic and Communication Engineering, Military Institute of Science and Technology (MIST)"
  ],
  "article_type": null,
  "arxiv": null,
  "author_total": 2,
  "authors": [
    {
      "affs": [
        0
      ],
      "name": "Mahfuzur Rahman Kabbo"
    },
    {
      "affs": [
        0
      ],
      "name": "Md. Tawfiq Amin"
    }
  ],
  "bibtex": "https://research.draconitic.com/paper/547f2zk4sgmsq.bib",
  "cited_by": 0,
  "doi": "10.1007/s44291-026-00304-w",
  "fulltext_url": "https://doi.org/10.1007/s44291-026-00304-w",
  "id": "547f2zk4sgmsq",
  "issns": [
    "2948-1600"
  ],
  "landing_url": "https://doi.org/10.1007/s44291-026-00304-w",
  "language": "en",
  "licence": "CC-BY",
  "licence_label": "CC BY",
  "licence_source": "journal",
  "licence_url": "https://creativecommons.org/licenses/by/4.0/",
  "metadata_licence": null,
  "native_subjects": [
    [
      "lcc",
      "QA1-939"
    ],
    [
      "lcc",
      "TK1-9971"
    ],
    [
      "openalex",
      "2208|Low-power high-performance VLSI design"
    ]
  ],
  "openalex": "W7223247907",
  "pdf_url": "https://link.springer.com/content/pdf/10.1007/s44291-026-00304-w.pdf",
  "pmcid": null,
  "pmid": null,
  "published": "2026-10-25",
  "publisher": "Springer",
  "ris": "https://research.draconitic.com/paper/547f2zk4sgmsq.ris",
  "sources": [
    {
      "first_seen": "2026-10-30T13:45:47Z",
      "native_id": "9ff7f70727da4aaaa2379ef939c390a5",
      "source": "doaj",
      "url": "https://doi.org/10.1007/s44291-026-00304-w"
    }
  ],
  "subjects": [
    {
      "field": "mathematics",
      "origin": "lcc:QA1-939",
      "subfield": "general"
    }
  ],
  "title": "Topology-aware HVT MTCMOS power gating for power–delay optimization of cascaded transmission-gate MUX and DEMUX",
  "title_text": "Topology-aware HVT MTCMOS power gating for power–delay optimization of cascaded transmission-gate MUX and DEMUX",
  "type": "peer-reviewed",
  "updated_at": "2026-10-30T13:45:47Z",
  "url": "https://research.draconitic.com/paper/547f2zk4sgmsq",
  "venue": "Discover Electronics",
  "versions": []
}