{
  "abstract": "As the semiconductor industry transitions to the post-Moore paradigm, wafer warpage has become a critical quality issue in advanced packaging; particularly for 3D stacking and high-bandwidth memory manufacturing where die-level deformation can affect bonding quality, interconnect reliability, and yield. However, direct high-throughput measurement of individual chip warpage remains difficult in mass-production environments, while existing wafer-level metrology systems routinely provide dense 3D shape data at the wafer scale. This paper proposes a Bezier-surface-based Gaussian Process---known as Bezier-GP---for chips-on-wafer warpage modeling. The proposed framework combines wafer-level point-cloud metrology data with wafer-map layout information to construct chip-region-level Bezier surface patches, imposes continuity constraints between neighboring patches, and represents the resulting chips-on-wafer surface through a compact free-control-point vector. A GP is then introduced in this low-dimensional representation to model wafer-to-wafer variation, chip-region-level spatial dependence, and provide uncertainty quantification. Numerical experiments, using an ASC wafer-map layout, demonstrate that the proposed framework can reconstruct chips-on-wafer surfaces, preserve chip-region-level geometric interpretability, and recover population-level mean and covariance structures under a controlled multi-wafer simulation setting. The results suggest that Bezier-GP provides a measurement-driven statistical modeling foundation for connecting wafer-level metrology data to chip-region-level warpage analysis in semiconductor manufacturing.",
  "abstract_shown": true,
  "affiliations": [],
  "article_type": null,
  "arxiv": "2611.04280",
  "author_total": 3,
  "authors": [
    {
      "name": "Sangyup Lee"
    },
    {
      "name": "Xiao Liu"
    },
    {
      "name": "Jianjun Shi"
    }
  ],
  "bibtex": "https://research.draconitic.com/paper/5je1xwzy0mdq4.bib",
  "cited_by": 0,
  "doi": "10.48550/arxiv.2611.04280",
  "fulltext_url": null,
  "id": "5je1xwzy0mdq4",
  "issns": [],
  "landing_url": "https://arxiv.org/abs/2611.04280",
  "language": null,
  "licence": "CC-BY-NC-ND-4.0",
  "licence_label": "CC BY-NC-ND 4.0",
  "licence_source": "article",
  "licence_url": "http://creativecommons.org/licenses/by-nc-nd/4.0/",
  "metadata_licence": "CC0-1.0",
  "native_subjects": [
    [
      "arxiv",
      "stat.AP"
    ]
  ],
  "openalex": null,
  "pdf_url": "https://arxiv.org/pdf/2611.04280",
  "pmcid": null,
  "pmid": null,
  "published": "2026-11-03",
  "publisher": null,
  "ris": "https://research.draconitic.com/paper/5je1xwzy0mdq4.ris",
  "sources": [
    {
      "first_seen": "2026-11-04T15:21:34Z",
      "native_id": "2611.04280",
      "source": "arxiv",
      "url": "https://arxiv.org/abs/2611.04280"
    }
  ],
  "subjects": [
    {
      "field": "mathematics",
      "origin": "arxiv:stat.AP",
      "subfield": "statistics"
    }
  ],
  "title": "Bezier-GP: Bezier-Surface-Based Gaussian Process for Chips-on-Wafer Warpage Modeling",
  "title_text": "Bezier-GP: Bezier-Surface-Based Gaussian Process for Chips-on-Wafer Warpage Modeling",
  "type": "preprint",
  "updated_at": "2026-11-06T18:21:10Z",
  "url": "https://research.draconitic.com/paper/5je1xwzy0mdq4",
  "venue": "arXiv",
  "versions": []
}