{
  "abstract": "Inverse design has emerged as a powerful strategy for realizing compact photonic devices; however, its application to logic operations remains constrained by challenges in physical interpretability, architectural generality, and experimental validation. This work introduces an experimentally validated, unified, and physics-driven inverse design framework that implements all fundamental Boolean logic gates within a single silicon photonic architecture. Devices are fabricated within a 2 x 2 um^2 design region on a silicon-on-insulator platform, representing one of the smallest areas reported for photonic logic elements. By integrating amplitude, phase, and energy conservation into a composite figure of merit, the proposed approach enables direct control over constructive and destructive interference. Consequently, all logic functions, including XOR and three-input NAND/NOR operations, are achieved using a standardized configuration with two logical inputs and a bias port. Experimental results exhibit good agreement with numerical simulations across the C-band, confirming both the predictive accuracy and fabrication robustness of the method. Performance benchmarking reveals competitive contrast ratios compared to previous implementations, while providing a unified and scalable design strategy. These findings establish a physically interpretable and experimentally validated paradigm for inverse-designed photonic logic, advancing the development of compact, integrated optical computing systems.",
  "abstract_shown": true,
  "affiliations": [],
  "article_type": null,
  "arxiv": "2609.05734",
  "author_total": 7,
  "authors": [
    {
      "name": "Ary Portes"
    },
    {
      "name": "Narges Dalvand"
    },
    {
      "name": "Felipe M. F. Teixeira"
    },
    {
      "name": "Omar P Vilela Neto"
    },
    {
      "name": "Julian L. Pita Ruiz"
    },
    {
      "name": "Michael Menard"
    },
    {
      "name": "Jhonattan C. Ramirez"
    }
  ],
  "bibtex": "https://research.draconitic.com/paper/5r6t36b29ngfj.bib",
  "cited_by": 0,
  "doi": "10.48550/arxiv.2609.05734",
  "fulltext_url": null,
  "id": "5r6t36b29ngfj",
  "issns": [],
  "landing_url": "https://arxiv.org/abs/2609.05734",
  "language": null,
  "licence": "CC-BY-NC-ND-4.0",
  "licence_label": "CC BY-NC-ND 4.0",
  "licence_source": "article",
  "licence_url": "http://creativecommons.org/licenses/by-nc-nd/4.0/",
  "metadata_licence": "CC0-1.0",
  "native_subjects": [
    [
      "arxiv",
      "eess.SP"
    ],
    [
      "arxiv",
      "physics.optics"
    ],
    [
      "openalex",
      "2208|Photonic and Optical Devices"
    ]
  ],
  "openalex": "W7212044562",
  "pdf_url": "https://arxiv.org/pdf/2609.05734",
  "pmcid": null,
  "pmid": null,
  "published": "2026-09-04",
  "publisher": null,
  "ris": "https://research.draconitic.com/paper/5r6t36b29ngfj.ris",
  "sources": [
    {
      "first_seen": "2026-10-30T12:19:48Z",
      "native_id": "2609.05734",
      "source": "arxiv",
      "url": "https://arxiv.org/abs/2609.05734"
    }
  ],
  "subjects": [
    {
      "field": "physics",
      "origin": "arxiv:physics.optics",
      "subfield": "optics-photonics"
    }
  ],
  "title": "Phase-aware Inverse Design for Silicon Photonic Logic Gates",
  "title_text": "Phase-aware Inverse Design for Silicon Photonic Logic Gates",
  "type": "preprint",
  "updated_at": "2026-10-30T12:19:48Z",
  "url": "https://research.draconitic.com/paper/5r6t36b29ngfj",
  "venue": "arXiv",
  "versions": []
}