{
  "abstract": "High qubit overhead is a key bottleneck for fault-tolerant quantum computation. Quantum low-density parity-check (qLDPC) codes offer high encoding efficiency but typically require non-local connectivity in every syndrome extraction cycle, incurring additional physical errors and implementation complexity. We introduce a hierarchical logical processor (HLP) architecture that implements a high-rate quantum CSS code with distance-$d_{0}$ rotated surface codes (RSC), allowing long-range connectivity to be used only once every $Θ(d_{0})$ rounds of surface-code syndrome extraction. HLPs introduce elongated RSC patches called shuttle buses. Using transversal hybrid-unit CNOT gates, a single shuttle bus can simultaneously couple to multiple standard RSC patches. This capability enables efficient level-1 syndrome extraction with suppressed level-1 error correlations and supports highly parallel logical Pauli measurements. We perform circuit-level simulations of several concrete HLP constructions and benchmark both logical memory and logical Pauli measurement performance. At a physical error rate of $10^{-3}$, a hierarchical logical processor can achieve 3-4 times higher qubit efficiency than the rotated surface code and 20-30 times shorter logical error-correction cycle times than the yoked surface code.",
  "abstract_shown": true,
  "affiliations": [],
  "article_type": null,
  "arxiv": "2606.22594",
  "author_total": 4,
  "authors": [
    {
      "name": "Zi-Han Chen"
    },
    {
      "name": "Ming-Cheng Chen"
    },
    {
      "name": "Chao-Yang Lu"
    },
    {
      "name": "Jian-Wei Pan"
    }
  ],
  "bibtex": "https://research.draconitic.com/paper/5w8q24d89s9wa.bib",
  "cited_by": 0,
  "doi": "10.48550/arxiv.2606.22594",
  "fulltext_url": null,
  "id": "5w8q24d89s9wa",
  "issns": [],
  "landing_url": "https://arxiv.org/abs/2606.22594",
  "language": null,
  "licence": "LicenseRef-arXiv-nonexclusive-1.0",
  "licence_label": "arXiv licence",
  "licence_source": "article",
  "licence_url": "http://arxiv.org/licenses/nonexclusive-distrib/1.0/",
  "metadata_licence": "CC0-1.0",
  "native_subjects": [
    [
      "arxiv",
      "quant-ph"
    ],
    [
      "openalex",
      "1702|Quantum Computing Algorithms and Architecture"
    ]
  ],
  "openalex": "W7165666009",
  "pdf_url": "https://arxiv.org/pdf/2606.22594",
  "pmcid": null,
  "pmid": null,
  "published": "2026-10-01",
  "publisher": null,
  "ris": "https://research.draconitic.com/paper/5w8q24d89s9wa.ris",
  "sources": [
    {
      "first_seen": "2026-10-30T12:26:03Z",
      "native_id": "2606.22594",
      "source": "arxiv",
      "url": "https://arxiv.org/abs/2606.22594"
    }
  ],
  "subjects": [
    {
      "field": "physics",
      "origin": "arxiv:quant-ph",
      "subfield": "quantum"
    }
  ],
  "title": "Hierarchical Quantum Logical Processor with Amortized Long-Range Connectivity",
  "title_text": "Hierarchical Quantum Logical Processor with Amortized Long-Range Connectivity",
  "type": "preprint",
  "updated_at": "2026-10-30T12:26:03Z",
  "url": "https://research.draconitic.com/paper/5w8q24d89s9wa",
  "venue": "arXiv",
  "versions": []
}