{
  "abstract": "Interleaved randomized benchmarking (IRB) provides a scalable estimate of a gate's error rate, but its standard guarantees require the interleaved gate to be Clifford~\\cite{Magesan2012Interleaved,magesan2012characterizing}. In superconducting processors, many non-Clifford phase gates in compiled circuits are implemented virtually as software-defined frame updates rather than as additional control pulses~\\cite{mckay2017efficient}. This raises the question of whether inserting or removing such virtual phases measurably changes IRB error estimates. We introduce \\emph{phase-altered interleaved randomized benchmarking} (PA-IRB), a paired-IRB diagnostic protocol comparing phase-stripped and phase-dressed Clifford interleaving gates derived from the same compiled implementation. PA-IRB reports $Δr=r_d-r_s$ with combined uncertainty to test whether virtual phase gates affect the extracted IRB decay beyond statistical error. As a case study, we apply PA-IRB to a compiled Toffoli gate executed on IBM superconducting processors, where the constituent $T/T^\\dagger$ gates are implemented as virtual $Z$ rotations. Across tested calibration runs, $Δr$ is consistent with zero within uncertainty, indicating that virtual phase addition or removal does not measurably alter the IRB-derived error estimate under the employed compilation and execution stack. More generally, PA-IRB provides a lightweight, abstraction-aware diagnostic for benchmarking workflows involving software-defined phase operations. The same paired comparison can also be used to place operational bounds on the contribution of non-Clifford components to the compiled gate error, even when those components are physically executed rather than implemented virtually.",
  "abstract_shown": true,
  "affiliations": [],
  "article_type": null,
  "arxiv": "2606.30327",
  "author_total": 3,
  "authors": [
    {
      "name": "Simona K. Grigorova"
    },
    {
      "name": "Nikolay V. Vitanov"
    },
    {
      "name": "Boyan T. Torosov"
    }
  ],
  "bibtex": "https://research.draconitic.com/paper/60p6tm3tgkar4.bib",
  "cited_by": 0,
  "doi": "10.48550/arxiv.2606.30327",
  "fulltext_url": null,
  "id": "60p6tm3tgkar4",
  "issns": [],
  "landing_url": "https://arxiv.org/abs/2606.30327",
  "language": null,
  "licence": "LicenseRef-arXiv-nonexclusive-1.0",
  "licence_label": "arXiv licence",
  "licence_source": "article",
  "licence_url": "http://arxiv.org/licenses/nonexclusive-distrib/1.0/",
  "metadata_licence": "CC0-1.0",
  "native_subjects": [
    [
      "arxiv",
      "quant-ph"
    ],
    [
      "openalex",
      "1702|Quantum Computing Algorithms and Architecture"
    ]
  ],
  "openalex": "W7166718855",
  "pdf_url": "https://arxiv.org/pdf/2606.30327",
  "pmcid": null,
  "pmid": null,
  "published": "2026-10-01",
  "publisher": null,
  "ris": "https://research.draconitic.com/paper/60p6tm3tgkar4.ris",
  "sources": [
    {
      "first_seen": "2026-10-30T12:26:45Z",
      "native_id": "2606.30327",
      "source": "arxiv",
      "url": "https://arxiv.org/abs/2606.30327"
    }
  ],
  "subjects": [
    {
      "field": "physics",
      "origin": "arxiv:quant-ph",
      "subfield": "quantum"
    }
  ],
  "title": "Phase-Altered Interleaved Randomized Benchmarking for Compiled Non-Clifford Gates",
  "title_text": "Phase-Altered Interleaved Randomized Benchmarking for Compiled Non-Clifford Gates",
  "type": "preprint",
  "updated_at": "2026-10-30T12:26:45Z",
  "url": "https://research.draconitic.com/paper/60p6tm3tgkar4",
  "venue": "arXiv",
  "versions": []
}