{
  "abstract": "Wiring and bandwidth bottlenecks between a quantum processor and room-temperature electronics can be reduced by placing digital control at the cryogenic stage, but commercial foundry standard-cell libraries are not specified for operation at 4 K. A cryogenic recharacterization flow is therefore developed for a commercial 22 nm FD-SOI foundry standard-cell library using commercially available cryogenic compact-device models, while retaining the original cell circuits, layouts, logic functions, and implementation semantics and remaining compatible with the commercial synthesis, place-and-route, and signoff methodology used at room temperature. Body-bias dependence is quantified over 38,640 matched slew/load points at zero, +/-0.9 V, and +/-1.8 V body bias. Relative to full bias, zero-bias operation increases the median rising and falling delays by 38.6x and 33.0x, while approximately 90% of transitions exceed the foundry-defined maximum-transition envelope. The 0.8 V-to-0.4 V level shifter is even more sensitive to body bias: its worst-case falling delay decreases from 30.6 ns at zero bias to 0.56 ns at +/-1.8 V. For the outbound 0.4 V-to-0.8 V crossing, driving the 0.8 V receiver without a level shifter dissipates 57.7 uW of static power per bit at full bias, against 0.196 nW when level-shifted. In post-route analysis of the unchanged extracted physical database of a fabricated 32-bit ALU, the register-to-register setup boundary increases from 1.3 MHz at zero bias to 37.9 MHz at +/-0.9 V and 132.9 MHz at +/-1.8 V.",
  "abstract_shown": true,
  "affiliations": [],
  "article_type": null,
  "arxiv": "2610.25498",
  "author_total": 9,
  "authors": [
    {
      "name": "Mohamed Gharib"
    },
    {
      "name": "Rami Rasheedi"
    },
    {
      "name": "Salma Abdelzaher"
    },
    {
      "name": "Henry Shi"
    },
    {
      "name": "Mike Hammer"
    },
    {
      "name": "Llorenç Fanals-i-Batllori"
    },
    {
      "name": "Aldo Pena Perez"
    },
    {
      "name": "Antonino Miceli"
    },
    {
      "name": "Inna Partin-Vaisband"
    }
  ],
  "bibtex": "https://research.draconitic.com/paper/9sr6x57a1050a.bib",
  "cited_by": 0,
  "doi": "10.48550/arxiv.2610.25498",
  "fulltext_url": null,
  "id": "9sr6x57a1050a",
  "issns": [],
  "landing_url": "https://arxiv.org/abs/2610.25498",
  "language": null,
  "licence": "CC-BY-4.0",
  "licence_label": "CC BY 4.0",
  "licence_source": "article",
  "licence_url": "http://creativecommons.org/licenses/by/4.0/",
  "metadata_licence": "CC0-1.0",
  "native_subjects": [
    [
      "arxiv",
      "cs.AR"
    ],
    [
      "arxiv",
      "quant-ph"
    ],
    [
      "openalex",
      "2208|Low-power high-performance VLSI design"
    ]
  ],
  "openalex": "W7222997753",
  "pdf_url": "https://arxiv.org/pdf/2610.25498",
  "pmcid": null,
  "pmid": null,
  "published": "2026-10-18",
  "publisher": null,
  "ris": "https://research.draconitic.com/paper/9sr6x57a1050a.ris",
  "sources": [
    {
      "first_seen": "2026-10-30T12:30:52Z",
      "native_id": "2610.25498",
      "source": "arxiv",
      "url": "https://arxiv.org/abs/2610.25498"
    }
  ],
  "subjects": [
    {
      "field": "physics",
      "origin": "arxiv:quant-ph",
      "subfield": "quantum"
    }
  ],
  "title": "Cryogenic Recharacterization of a Commercial 22 nm FD-SOI Foundry Standard-Cell Library",
  "title_text": "Cryogenic Recharacterization of a Commercial 22 nm FD-SOI Foundry Standard-Cell Library",
  "type": "preprint",
  "updated_at": "2026-10-30T12:33:41Z",
  "url": "https://research.draconitic.com/paper/9sr6x57a1050a",
  "venue": "arXiv",
  "versions": []
}