{
  "abstract": "Scaling superconducting quantum processors requires interconnects that provide both non-local connectivity and parallel entangling operations. While current quantum routers offer greater connectivity than nearest-neighbour topologies, their support for parallel, independently addressable two-qubit gates remains fundamentally limited, imposing severe compilation overheads that constitute a critical bottleneck. Here we introduce a bus-based reconfigurable quantum router that enables parallel controlled-$Z$ (CZ) gates for modular superconducting processors. Constructed from a flux-tunable SQUID network, the router selectively connects interface qubits to two shared buses, allowing destructive interference to suppress idle interactions while supporting two disjoint CZ gates in parallel. Full-system Hamiltonian simulations yield parallel-gate infidelities ranging from $7.9\\times10^{-4}$ to $1.8\\times10^{-3}$ under the operating conditions considered, and an open-system analysis identifies the coherence requirements for high-fidelity operation. We further assess the circuit-level consequences using hardware-aware compilation and resource-constrained scheduling. For the 36-qubit quantum Fourier transform (QFT), QAOA-MaxCut, and random-pairing circuits, the router reduces the median SWAP count by up to $34\\%$ and the native CZ count by up to $20\\%$ relative to a matched two-dimensional grid. Circuit-depth reductions are workload-dependent, reaching $20\\%$ for QAOA-MaxCut but remaining negligible for the QFT despite its lower gate count. These results show that enhanced connectivity and schedulable parallelism provide complementary benefits for connectivity-intensive algorithms, establishing the router as a compiler-visible hardware resource and providing a scalable architectural pathway toward constructing highly connected modular superconducting quantum processors.",
  "abstract_shown": true,
  "affiliations": [],
  "article_type": null,
  "arxiv": "2609.28881",
  "author_total": 10,
  "authors": [
    {
      "name": "Benzheng Yuan"
    },
    {
      "name": "chaojie Zhang"
    },
    {
      "name": "Yangyang Fei"
    },
    {
      "name": "Chuanbing Han"
    },
    {
      "name": "Haoran He"
    },
    {
      "name": "Huihui Sun"
    },
    {
      "name": "Bo Zhao"
    },
    {
      "name": "Fudong Liu"
    },
    {
      "name": "Weilong Wang"
    },
    {
      "name": "Zheng Shan"
    }
  ],
  "bibtex": "https://research.draconitic.com/paper/b7s37rjnf94r3.bib",
  "cited_by": 0,
  "doi": "10.48550/arxiv.2609.28881",
  "fulltext_url": null,
  "id": "b7s37rjnf94r3",
  "issns": [],
  "landing_url": "https://arxiv.org/abs/2609.28881",
  "language": null,
  "licence": "LicenseRef-arXiv-nonexclusive-1.0",
  "licence_label": "arXiv licence",
  "licence_source": "article",
  "licence_url": "http://arxiv.org/licenses/nonexclusive-distrib/1.0/",
  "metadata_licence": "CC0-1.0",
  "native_subjects": [
    [
      "arxiv",
      "quant-ph"
    ],
    [
      "openalex",
      "1702|Quantum Information and Cryptography"
    ]
  ],
  "openalex": "W7214377940",
  "pdf_url": "https://arxiv.org/pdf/2609.28881",
  "pmcid": null,
  "pmid": null,
  "published": "2026-09-30",
  "publisher": null,
  "ris": "https://research.draconitic.com/paper/b7s37rjnf94r3.ris",
  "sources": [
    {
      "first_seen": "2026-10-30T12:25:48Z",
      "native_id": "2609.28881",
      "source": "arxiv",
      "url": "https://arxiv.org/abs/2609.28881"
    }
  ],
  "subjects": [
    {
      "field": "physics",
      "origin": "arxiv:quant-ph",
      "subfield": "quantum"
    }
  ],
  "title": "Reconfigurable Bus-based Quantum Router for Modular Superconducting Processors",
  "title_text": "Reconfigurable Bus-based Quantum Router for Modular Superconducting Processors",
  "type": "preprint",
  "updated_at": "2026-10-30T12:25:48Z",
  "url": "https://research.draconitic.com/paper/b7s37rjnf94r3",
  "venue": "arXiv",
  "versions": []
}