{
  "abstract": "Ultra-low-latency machine learning and data processing pipelines operating on the sub-microsecond level often contain static dataflow kernels that require fine-grained bitwidth control, arithmetic optimization, and fast hardware performance estimation. This works introduce Alkaid, a free and open source domain specific compiler that translates sub-microsecond latency dataflow kernels into platform agnostic Register Transfer Level (RTL) or High-Level Synthesis (HLS)-ready code in seconds. Alkaid targets ultra-low-latency ML pipelines, especially those addressed by existing ML-to-hardware flows such as \\texttt{hls4ml}, while also supporting the surrounding pre-processing, post-processing, and control logic. At its core, Alkaid uses an arithmetic centric intermediate representation, Alkaid Low-level IR (ALIR), to preserve fixed-point semantics, heterogeneous bitwidths, and operation level structure for optimization and code generation. Alkaid further provides comprehensive hardware-aware optimization passes and an interpretable white-box analytical performance model for rapid design space exploration without synthesis in the loop. Across representative ML workloads, including MLPs, GNNs, and transformers, Alkaid achieves 20-30\\% lower LUT usage than the best prior flows for bit-exact equivalent designs, with up to 40\\% lower latency in some cases. Beyond typical neural networks, Alkaid achieves comparable performance to the state-of-the-art method for synthesizing boosted decision trees, while also enabling the implementation and integration of non-ML kernels such as sorting networks and histograms.",
  "abstract_shown": true,
  "affiliations": [],
  "article_type": null,
  "arxiv": "2610.04808",
  "author_total": 6,
  "authors": [
    {
      "name": "Chang Sun"
    },
    {
      "name": "Zhiqiang Que"
    },
    {
      "name": "Dimitrios Danopoulos"
    },
    {
      "name": "Maurizio Pierini"
    },
    {
      "name": "Wayne Luk"
    },
    {
      "name": "Maria Spiropulu"
    }
  ],
  "bibtex": "https://research.draconitic.com/paper/dyygaq6jxhj3r.bib",
  "cited_by": 0,
  "doi": "10.48550/arxiv.2610.04808",
  "fulltext_url": null,
  "id": "dyygaq6jxhj3r",
  "issns": [],
  "landing_url": "https://arxiv.org/abs/2610.04808",
  "language": null,
  "licence": "CC-BY-4.0",
  "licence_label": "CC BY 4.0",
  "licence_source": "article",
  "licence_url": "http://creativecommons.org/licenses/by/4.0/",
  "metadata_licence": "CC0-1.0",
  "native_subjects": [
    [
      "arxiv",
      "cs.AR"
    ],
    [
      "arxiv",
      "hep-ex"
    ],
    [
      "openalex",
      "1708|Embedded Systems Design Techniques"
    ]
  ],
  "openalex": "W7220716858",
  "pdf_url": "https://arxiv.org/pdf/2610.04808",
  "pmcid": null,
  "pmid": null,
  "published": "2026-10-03",
  "publisher": null,
  "ris": "https://research.draconitic.com/paper/dyygaq6jxhj3r.ris",
  "sources": [
    {
      "first_seen": "2026-10-30T12:27:01Z",
      "native_id": "2610.04808",
      "source": "arxiv",
      "url": "https://arxiv.org/abs/2610.04808"
    }
  ],
  "subjects": [
    {
      "field": "physics",
      "origin": "arxiv:hep-ex",
      "subfield": "high-energy"
    }
  ],
  "title": "Alkaid: A Compiler Framework for Ultra-Low-Latency Kernels on Hardware",
  "title_text": "Alkaid: A Compiler Framework for Ultra-Low-Latency Kernels on Hardware",
  "type": "preprint",
  "updated_at": "2026-10-30T12:27:01Z",
  "url": "https://research.draconitic.com/paper/dyygaq6jxhj3r",
  "venue": "arXiv",
  "versions": []
}