{
  "abstract": "YOLOv3-tiny is widely used in edge-oriented object detection, but its deployment on resource-constrained platforms is limited by high computational cost and the limited flexibility of conventional processors. This paper presents a RISC-V-based acceleration framework for YOLOv3-tiny inference that combines a tightly coupled CPU-accelerator architecture with runtime-reconfigurable hardware support. A Hummingbird E203 core is integrated with a dedicated accelerator through the NICE interface, and 11 custom instructions are introduced for data movement, convolution control, and post-processing. The hardware adopts a runtime-reconfigurable systolic array supporting multiple convolution kernel sizes, together with activation, pooling, fully connected, and detection-oriented post-processing modules. The design is implemented on an Artix-7 FPGA and evaluated using a hardware-oriented YOLOv3-tiny workload, supplemented by module-level analysis and same-platform baseline comparisons. Experimental results show a 79.5% reduction in convolution execution time and a 4.89 $$\\times$$ speed-up over the baseline RISC-V processor. Hardware-supported post-processing further reduces the cycle cost of sorting and IoU-related computation by 60.55% and 45.44%, respectively. These results demonstrate the effectiveness of the proposed processor-coupled acceleration architecture for YOLOv3-tiny-based detection inference on edge platforms.",
  "abstract_shown": true,
  "affiliations": [
    "Tongda College, Nanjing University of Posts and Telecommunications",
    "School of Computer Science, Nanjing University of Posts and Telecommunications",
    "College of Information Engineering, Yangzhou Polytechnic Institute"
  ],
  "article_type": null,
  "arxiv": null,
  "author_total": 4,
  "authors": [
    {
      "affs": [
        0
      ],
      "name": "Shuya Wang"
    },
    {
      "affs": [
        1
      ],
      "name": "Xuecong Chen"
    },
    {
      "affs": [
        0
      ],
      "name": "Detao Nie"
    },
    {
      "affs": [
        2
      ],
      "name": "Fujun Wang"
    }
  ],
  "bibtex": "https://research.draconitic.com/paper/ea05ay7a78by0.bib",
  "cited_by": 0,
  "doi": "10.1038/s41598-026-60759-5",
  "fulltext_url": "https://doi.org/10.1038/s41598-026-60759-5",
  "id": "ea05ay7a78by0",
  "issns": [
    "2045-2322"
  ],
  "landing_url": "https://doi.org/10.1038/s41598-026-60759-5",
  "language": "en",
  "licence": "CC-BY",
  "licence_label": "CC BY",
  "licence_source": "journal",
  "licence_url": "https://creativecommons.org/licenses/by/4.0/",
  "metadata_licence": null,
  "native_subjects": [
    [
      "lcc",
      "Q"
    ],
    [
      "lcc",
      "R"
    ],
    [
      "openalex",
      "1708|Embedded Systems Design Techniques"
    ]
  ],
  "openalex": "W7169875884",
  "pdf_url": "https://www.nature.com/articles/s41598-026-60759-5_reference.pdf",
  "pmcid": null,
  "pmid": null,
  "published": "2026-07-01",
  "publisher": "Nature Portfolio",
  "ris": "https://research.draconitic.com/paper/ea05ay7a78by0.ris",
  "sources": [
    {
      "first_seen": "2026-10-30T13:45:45Z",
      "native_id": "6175beca97834b0fb46bc42cc672f97a",
      "source": "doaj",
      "url": "https://doi.org/10.1038/s41598-026-60759-5"
    }
  ],
  "subjects": [
    {
      "field": "medicine",
      "origin": "lcc:R",
      "subfield": "general"
    }
  ],
  "title": "RISC-V-based YOLOv3-tiny acceleration with runtime-reconfigurable systolic arrays and custom instructions",
  "title_text": "RISC-V-based YOLOv3-tiny acceleration with runtime-reconfigurable systolic arrays and custom instructions",
  "type": "peer-reviewed",
  "updated_at": "2026-10-30T13:45:45Z",
  "url": "https://research.draconitic.com/paper/ea05ay7a78by0",
  "venue": "Scientific Reports",
  "versions": []
}