{
  "abstract": "For the first time, we proposed a novel stacking technology for DRAM scaling by flipping and backside processes, making full use of DRAM wafer's backside and investigating it on both 4F2 and 3D-DRAM. For 4F2 VCT, 2F2 Flip VCT featuring self-aligned back-to-back stacked 1T1C bitcell, with various BL and WL configurations, were studied and key process modules such as self-aligned stacked vertical channel, BL and WL formations, wafer bonding and flipping, substrate thinning and low-R Co storage node (SN) were successfully developed, addressing the potential thermal, misalign and parasitic concerns in the Flip VCT process. A full DRAM DTCO framework was also established from device to mat and chip level. Compared to 4F2 VCT DRAM with the same mat size, 2F2 FVCT delivers 27.5% less parasitics, 11% better sense margin, 16.3% higher charge sharing (CS) speed and 50% less area. For 3D-DRAM, a brand-new flip WL staircase design with peripheral circuit innovations was studied and proved to have 25% density gain, 15.1% faster turn-on speed and 6.8% less CS time, proving further extendibility of flip technology on DRAM.",
  "abstract_shown": true,
  "affiliations": [],
  "article_type": null,
  "arxiv": "2609.14464",
  "author_total": 22,
  "authors": [
    {
      "name": "Yu Liu"
    },
    {
      "name": "Xinyue He"
    },
    {
      "name": "Yanbang Chu"
    },
    {
      "name": "Siyuan Liu"
    },
    {
      "name": "Jianxiang Jin"
    },
    {
      "name": "Fangcheng Sun"
    },
    {
      "name": "Yuyang Qiao"
    },
    {
      "name": "Xu Tian"
    },
    {
      "name": "Lan Li"
    },
    {
      "name": "Baokang Peng"
    },
    {
      "name": "Lining Zhang"
    },
    {
      "name": "Xing Wu"
    },
    {
      "name": "Pengpeng Ren"
    },
    {
      "name": "Zhigang Ji"
    },
    {
      "name": "Zongwei Wang"
    },
    {
      "name": "Lijie Zhang"
    },
    {
      "name": "Xinwei Wan"
    },
    {
      "name": "Weihai Bu"
    },
    {
      "name": "Ming Li"
    },
    {
      "name": "Runsheng Wang"
    },
    {
      "name": "Heng Wu"
    },
    {
      "name": "Ru Huang"
    }
  ],
  "bibtex": "https://research.draconitic.com/paper/efdy0e18w8bsy.bib",
  "cited_by": 0,
  "doi": "10.48550/arxiv.2609.14464",
  "fulltext_url": null,
  "id": "efdy0e18w8bsy",
  "issns": [],
  "landing_url": "https://arxiv.org/abs/2609.14464",
  "language": null,
  "licence": "LicenseRef-arXiv-nonexclusive-1.0",
  "licence_label": "arXiv licence",
  "licence_source": "article",
  "licence_url": "http://arxiv.org/licenses/nonexclusive-distrib/1.0/",
  "metadata_licence": "CC0-1.0",
  "native_subjects": [
    [
      "arxiv",
      "cond-mat.mes-hall"
    ],
    [
      "openalex",
      "2208|Advancements in Semiconductor Devices and Circuit Design"
    ]
  ],
  "openalex": "W7213337255",
  "pdf_url": "https://arxiv.org/pdf/2609.14464",
  "pmcid": null,
  "pmid": null,
  "published": "2026-09-13",
  "publisher": null,
  "ris": "https://research.draconitic.com/paper/efdy0e18w8bsy.ris",
  "sources": [
    {
      "first_seen": "2026-10-30T12:21:25Z",
      "native_id": "2609.14464",
      "source": "arxiv",
      "url": "https://arxiv.org/abs/2609.14464"
    }
  ],
  "subjects": [
    {
      "field": "physics",
      "origin": "arxiv:cond-mat.mes-hall",
      "subfield": "condensed-matter"
    }
  ],
  "title": "First Demonstration of Flip DRAM from Process, Architecture to System to Push DRAM Scaling beyond 4F2: 2F2 Self-aligned Flip Vertical Channel Transistor (FVCT) DRAM and Flip WL (FWL) 3D-DRAM",
  "title_text": "First Demonstration of Flip DRAM from Process, Architecture to System to Push DRAM Scaling beyond 4F2: 2F2 Self-aligned Flip Vertical Channel Transistor (FVCT) DRAM and Flip WL (FWL) 3D-DRAM",
  "type": "preprint",
  "updated_at": "2026-10-30T12:21:25Z",
  "url": "https://research.draconitic.com/paper/efdy0e18w8bsy",
  "venue": "arXiv",
  "versions": []
}