{
  "abstract": "Long-running quantum computations, including error-corrected workloads, demand instruction availability, measurement-dependent control, and calibration updates. We present Time-Deterministic and Instruction-Dynamic Execution, an FPGA quantum-control processor supporting runtime revision at both instruction and parameter levels. Dynamic Instruction Parameter Update supplies one-shot, next-match patches before parameter capture, while Dynamic Instruction Stream Overwrite provides guarded replacement, logical deletion, and out-of-line insertion in eligible future regions of a resident program. A moving fetch-visibility guard coordinates instruction updates with execution, and event commitment isolates complete descriptors for independent hardware-timed dispatch. Revision applicability depends on update timing and execution progress; deterministic service applies to committed events under the stated scheduling conditions. The Xilinx ZCU102 implementation uses a 250-MHz control core and a 425-MHz timing/update domain. FPGA-resident measurements at the registered digital interfaces confirmed programmed-cycle dispatch for all tested descriptors committed at least one timing-domain cycle before their timestamps, with downstream ready and the stated FIFO ordering conditions. Separate tests confirmed post-commit timestamp and payload invariance. The minimum all-success mapped DIPU margin was four control-domain cycles, and a replacement of L instruction words completed in L+5 update-domain cycles under continuous payload delivery. Within the tested guard-distance range, rejected DISO requests reported an error and preserved the resident path, whereas all admitted revisions tested here executed complete revised sequences. These results provide a hardware execution basis for incorporating runtime-generated sequences and parameter corrections into precisely timed quantum computations with feedback.",
  "abstract_shown": true,
  "affiliations": [],
  "article_type": "Journal reference: Rev. Sci. Instrum. 97, 103204 (2026)",
  "arxiv": "2608.15173",
  "author_total": 3,
  "authors": [
    {
      "name": "Xiaoqin Luo"
    },
    {
      "name": "Jiayun Song"
    },
    {
      "name": "Xiaolu Su"
    }
  ],
  "bibtex": "https://research.draconitic.com/paper/f5tyyfjb7dy3v.bib",
  "cited_by": 0,
  "doi": "10.48550/arxiv.2608.15173",
  "fulltext_url": null,
  "id": "f5tyyfjb7dy3v",
  "issns": [],
  "landing_url": "https://arxiv.org/abs/2608.15173",
  "language": null,
  "licence": "LicenseRef-arXiv-nonexclusive-1.0",
  "licence_label": "arXiv licence",
  "licence_source": "article",
  "licence_url": "http://arxiv.org/licenses/nonexclusive-distrib/1.0/",
  "metadata_licence": "CC0-1.0",
  "native_subjects": [
    [
      "arxiv",
      "cs.AR"
    ],
    [
      "arxiv",
      "quant-ph"
    ],
    [
      "openalex",
      "1708|Embedded Systems Design Techniques"
    ]
  ],
  "openalex": "W7203676809",
  "pdf_url": "https://arxiv.org/pdf/2608.15173",
  "pmcid": null,
  "pmid": null,
  "published": "2026-11-03",
  "publisher": null,
  "ris": "https://research.draconitic.com/paper/f5tyyfjb7dy3v.ris",
  "sources": [
    {
      "first_seen": "2026-11-04T15:21:24Z",
      "native_id": "2608.15173",
      "source": "arxiv",
      "url": "https://arxiv.org/abs/2608.15173"
    }
  ],
  "subjects": [
    {
      "field": "physics",
      "origin": "arxiv:quant-ph",
      "subfield": "quantum"
    }
  ],
  "title": "Time-Deterministic and Instruction-Dynamic Execution: A field-programmable gate array quantum-control processor",
  "title_text": "Time-Deterministic and Instruction-Dynamic Execution: A field-programmable gate array quantum-control processor",
  "type": "preprint",
  "updated_at": "2026-11-06T18:21:01Z",
  "url": "https://research.draconitic.com/paper/f5tyyfjb7dy3v",
  "venue": "arXiv",
  "versions": [
    {
      "doi": "10.1063/5.0356629",
      "pid": null,
      "relation": "published-as",
      "title": null,
      "venue": null
    }
  ]
}