{
  "abstract": "Real-time track finding for displaced-muon signatures in the CMS Level-1 trigger must operate under strict fixed-latency constraints of 12.5 $μ$s while processing high-throughput detector data. Because muon hits map naturally onto sparse, irregular graphs, graph neural networks (GNNs) are attractive candidates; however, mapping message-passing models to field-programmable gate arrays (FPGAs) requires careful co-design of numerical precision, microarchitecture, and high-level synthesis (HLS) implementation. This work presents a reproducible, bit-exact workflow bridging GNN design and FPGA prototyping for fixed-latency inference. The methodology is demonstrated by implementing a two-layer GraphSAGE network onto an XCVU13P FPGA, using the Cora citation network as a fixed-size benchmark for firmware evaluation that decouples deployment feasibility from the physics task. Starting from a 32-bit floating-point reference that exceeds the available FPGA resource budget, we derive an integer-only datapath through post-training quantization (INT8 weights and activations, INT32 biases), a power-of-two scale approximation that replaces rescaling multipliers with arithmetic shifts, and data-driven bit-width narrowing. Every stage is validated bit-exactly against a Python integer emulator in Vitis HLS C-simulation. The optimized INT8 power-of-two design achieves an inference latency of 19 clock cycles (52.8 ns at the nominal 360 MHz clock) at 20\\% DSP, 6\\% FF, and 27\\% LUT utilization, with 75.0$\\pm$1.1\\% accuracy compared to the 78.0$\\pm$0.8\\% for FP32. Accuracy is reported as the average across multiple training seeds. The resulting workflow establishes a concrete, transferable path toward fixed-latency GNN-based track reconstruction in the CMS Level-1 trigger.",
  "abstract_shown": true,
  "affiliations": [],
  "article_type": null,
  "arxiv": "2609.28144",
  "author_total": 4,
  "authors": [
    {
      "name": "Andrea Cardini"
    },
    {
      "name": "Pelayo Leguina"
    },
    {
      "name": "Elena Aller"
    },
    {
      "name": "Santiago Folgueras"
    }
  ],
  "bibtex": "https://research.draconitic.com/paper/fnwfzvxwcq55r.bib",
  "cited_by": 0,
  "doi": "10.48550/arxiv.2609.28144",
  "fulltext_url": null,
  "id": "fnwfzvxwcq55r",
  "issns": [],
  "landing_url": "https://arxiv.org/abs/2609.28144",
  "language": null,
  "licence": "LicenseRef-arXiv-nonexclusive-1.0",
  "licence_label": "arXiv licence",
  "licence_source": "article",
  "licence_url": "http://arxiv.org/licenses/nonexclusive-distrib/1.0/",
  "metadata_licence": "CC0-1.0",
  "native_subjects": [
    [
      "arxiv",
      "hep-ex"
    ],
    [
      "openalex",
      "1708|Embedded Systems Design Techniques"
    ]
  ],
  "openalex": "W7214238862",
  "pdf_url": "https://arxiv.org/pdf/2609.28144",
  "pmcid": null,
  "pmid": null,
  "published": "2026-09-23",
  "publisher": null,
  "ris": "https://research.draconitic.com/paper/fnwfzvxwcq55r.ris",
  "sources": [
    {
      "first_seen": "2026-10-30T12:23:56Z",
      "native_id": "2609.28144",
      "source": "arxiv",
      "url": "https://arxiv.org/abs/2609.28144"
    }
  ],
  "subjects": [
    {
      "field": "physics",
      "origin": "arxiv:hep-ex",
      "subfield": "high-energy"
    }
  ],
  "title": "Integer Quantization of Graph Neural Networks for Real-Time FPGA Track Finding",
  "title_text": "Integer Quantization of Graph Neural Networks for Real-Time FPGA Track Finding",
  "type": "preprint",
  "updated_at": "2026-10-30T12:23:56Z",
  "url": "https://research.draconitic.com/paper/fnwfzvxwcq55r",
  "venue": "arXiv",
  "versions": []
}