FPGA Implementation Based on the Short-Memory Principle: Analysis of a Lorenz-Type Systems Family
- 1Department of Electronics, Instituto Nacional de Astrofísica, Óptica y Electrónica (INAOE), Luis Enrique Erro No. 1, Santa María Tonantzintla, San Andrés Cholula 72840, Puebla, Mexico
Abstract
Fractional differential equations and fractional-order chaotic systems are attractive for secure communications, but the nonlocal memory of the Caputo derivative makes their digital implementation costly, so iterative methods are preferred for developing digital implementations of physical systems. This paper characterizes seven members of the Lorenz family (Lorenz, Chen, Burke–Shaw, Liu, Shimizu–Morioka, Lü, and Yang) and implements them on an FPGA using the short-memory principle. Starting from rectangular (REC) and predictor–corrector (PC) product-integration rules, we derive incremental iterative forms with a finite memory window suited to digital hardware. Largest Lyapunov exponent maps and bifurcation diagrams over fractional order and memory duration identify chaotic regimes for the Caputo case that, to our knowledge, have not been reported; for most systems, they stabilize once the window exceeds about 2 s. On a Cyclone V FPGA with a common Q1.11.20 fixed-point format, each architecture lets you select any of the seven systems and a memory depth of 1–1000 samples without resynthesis. For a 2 s window, REC uses fewer resources (3258 ALMs, 60 DSP blocks), whereas PC, thanks to its larger time step, reaches a higher estimated state-generation rate (330,457 versus 291,839 state vectors/s). Finally, 8-bit pseudorandom sequences extracted from the Lorenz system (1 Gbit per architecture) pass NIST SP 800-22 and the TestU01 Rabbit, Alphabit, and BlockAlphabit batteries. In addition, we present numerical simulations and their digital implementation to validate the numerical schemes.
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BibTeX
@article{garzongonzalez2026fpga,
title = {{FPGA Implementation Based on the Short-Memory Principle: Analysis of a Lorenz-Type Systems Family}},
author = {Jeferson Andrés Garzón-González and Oscar Martínez-Fuentes and Juan Manuel Torres-Arce and Omar Guillén-Fernández and Esteban Tlelo-Cuautle and Jose de Jesus Rangel-Magdaleno},
journal = {Fractal and Fractional},
year = {2026},
month = oct,
doi = {10.3390/fractalfract10110753},
url = {https://www.mdpi.com/2504-3110/10/11/753},
note = {CC BY 4.0},
}
RIS
TY - JOUR
TI - FPGA Implementation Based on the Short-Memory Principle: Analysis of a Lorenz-Type Systems Family
AU - Jeferson Andrés Garzón-González
AU - Oscar Martínez-Fuentes
AU - Juan Manuel Torres-Arce
AU - Omar Guillén-Fernández
AU - Esteban Tlelo-Cuautle
AU - Jose de Jesus Rangel-Magdaleno
PY - 2026
DA - 2026/10/28
JO - Fractal and Fractional
DO - 10.3390/fractalfract10110753
UR - https://www.mdpi.com/2504-3110/10/11/753
AB - Fractional differential equations and fractional-order chaotic systems are attractive for secure communications, but the nonlocal memory of the Caputo derivative makes their digital implementation costly, so iterative methods are preferred for developing digital implementations of physical systems. This paper characterizes seven members of the Lorenz family (Lorenz, Chen, Burke–Shaw, Liu, Shimizu–Morioka, Lü, and Yang) and implements them on an FPGA using the short-memory principle. Starting from rectangular (REC) and predictor–corrector (PC) product-integration rules, we derive incremental iterative forms with a finite memory window suited to digital hardware. Largest Lyapunov exponent maps and bifurcation diagrams over fractional order and memory duration identify chaotic regimes for the Caputo case that, to our knowledge, have not been reported; for most systems, they stabilize once the window exceeds about 2 s. On a Cyclone V FPGA with a common Q1.11.20 fixed-point format, each architecture lets you select any of the seven systems and a memory depth of 1–1000 samples without resynthesis. For a 2 s window, REC uses fewer resources (3258 ALMs, 60 DSP blocks), whereas PC, thanks to its larger time step, reaches a higher estimated state-generation rate (330,457 versus 291,839 state vectors/s). Finally, 8-bit pseudorandom sequences extracted from the Lorenz system (1 Gbit per architecture) pass NIST SP 800-22 and the TestU01 Rabbit, Alphabit, and BlockAlphabit batteries. In addition, we present numerical simulations and their digital implementation to validate the numerical schemes.
SN - 2504-3110
ER -