PreprintCC BY 4.0arXiv
Design and Analysis of a 2D Vernier Structure
Abstract
This paper presents the design and simulation of a 2D Vernier Time-to-Digital Converter (TDC) targeting less than 20 picosecond time resolution and 5-bit output resolution. The TDC comprises voltage-controlled delay buffers, NAND-based SR latches with reset functionality, and a calibration loop using a phase-frequency detector (PFD) and charge pump. The calibration loop dynamically adjusts delay mismatches to maintain consistent timing across process-voltage-temperature (PVT) corners, significantly improving linearity. Simulations show that the TDC achieves a resolution of 16.9 ps for tt corner and maintains DNL and INL below 0.5 LSB under all tested PVT conditions
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BibTeX
@misc{yildiz2026design,
title = {{Design and Analysis of a 2D Vernier Structure}},
author = {Hüsna Yildiz and Rick Helmer},
howpublished = {arXiv},
year = {2026},
month = sep,
doi = {10.48550/arxiv.2609.36083},
eprint = {2609.36083},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2609.36083},
note = {CC BY 4.0},
}
RIS
TY - UNPB
TI - Design and Analysis of a 2D Vernier Structure
AU - Hüsna Yildiz
AU - Rick Helmer
PY - 2026
DA - 2026/09/28
PB - arXiv
DO - 10.48550/arxiv.2609.36083
UR - https://arxiv.org/abs/2609.36083
AB - This paper presents the design and simulation of a 2D Vernier Time-to-Digital Converter (TDC) targeting less than 20 picosecond time resolution and 5-bit output resolution. The TDC comprises voltage-controlled delay buffers, NAND-based SR latches with reset functionality, and a calibration loop using a phase-frequency detector (PFD) and charge pump. The calibration loop dynamically adjusts delay mismatches to maintain consistent timing across process-voltage-temperature (PVT) corners, significantly improving linearity. Simulations show that the TDC achieves a resolution of 16.9 ps for tt corner and maintains DNL and INL below 0.5 LSB under all tested PVT conditions
ER -