QCORE: A Quantum-Computing-Oriented,Resource-Efficient Runtime Architecture with Lifecycle Coordination
Abstract
As quantum processors scale, online calibration, quantum error correction (QEC), and measurement-driven feedback require continuous classical processing and parameter updates. Sharing on-chip resources reduces hardware cost, but computation completion, the last parameter read, and result consumption occur at different times. Their dependencies must be managed separately while preserving quantum operations' real-time requirements. We present QCORE, a quantum-computing-oriented, resource-efficient runtime architecture that coordinates these lifecycles for safe resource reuse and parameter consistency. QCORE models resource occupancy, parameter protection, and consumer dependencies as independent lifecycles and provides three mechanisms: pre-use checks and parameter binding to verify timing, identity, and dependencies; access-aware protection through value snapshots, version references, or active-configuration windows; and joint admission of resource reservations and parameter installation. After request submission, hardware autonomously handles admission, protection, installation, and reclamation, reducing fine-grained Host coordination and providing a foundation for one Host to manage multiple controllers. We implement synthesizable RTL and validate FPGA timing at 100 MHz. Independent release reduces whole-program execution time by 16.83% in Ramsey calibration and QEC replay. Joint admission increases on-time completions from 5/15 to 15/15 under contention across five arrival phases. Under identical external deadlines, a shared NN backend reduces LUT usage by 12.28%-13.81% and DSP usage by 39.39% compared with two statically assigned backends. These results show that lifecycle coordination exploits inter-task timing slack for on-chip sharing, increasing service capacity under limited resources.
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BibTeX
@misc{li2026qcore,
title = {{QCORE: A Quantum-Computing-Oriented,Resource-Efficient Runtime Architecture with Lifecycle Coordination}},
author = {Heyue Li and Shaolin Xiang and Tian Tian and Qichun Liu and Tiefu Li and Zhihua Wang and Yanshu Guo and Hanjun Jiang},
howpublished = {arXiv},
year = {2026},
month = nov,
doi = {10.48550/arxiv.2608.06875},
eprint = {2608.06875},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2608.06875},
note = {CC BY-NC-SA 4.0},
}
RIS
TY - UNPB
TI - QCORE: A Quantum-Computing-Oriented,Resource-Efficient Runtime Architecture with Lifecycle Coordination
AU - Heyue Li
AU - Shaolin Xiang
AU - Tian Tian
AU - Qichun Liu
AU - Tiefu Li
AU - Zhihua Wang
AU - Yanshu Guo
AU - Hanjun Jiang
PY - 2026
DA - 2026/11/09
PB - arXiv
DO - 10.48550/arxiv.2608.06875
UR - https://arxiv.org/abs/2608.06875
AB - As quantum processors scale, online calibration, quantum error correction (QEC), and measurement-driven feedback require continuous classical processing and parameter updates. Sharing on-chip resources reduces hardware cost, but computation completion, the last parameter read, and result consumption occur at different times. Their dependencies must be managed separately while preserving quantum operations' real-time requirements. We present QCORE, a quantum-computing-oriented, resource-efficient runtime architecture that coordinates these lifecycles for safe resource reuse and parameter consistency. QCORE models resource occupancy, parameter protection, and consumer dependencies as independent lifecycles and provides three mechanisms: pre-use checks and parameter binding to verify timing, identity, and dependencies; access-aware protection through value snapshots, version references, or active-configuration windows; and joint admission of resource reservations and parameter installation. After request submission, hardware autonomously handles admission, protection, installation, and reclamation, reducing fine-grained Host coordination and providing a foundation for one Host to manage multiple controllers. We implement synthesizable RTL and validate FPGA timing at 100 MHz. Independent release reduces whole-program execution time by 16.83% in Ramsey calibration and QEC replay. Joint admission increases on-time completions from 5/15 to 15/15 under contention across five arrival phases. Under identical external deadlines, a shared NN backend reduces LUT usage by 12.28%-13.81% and DSP usage by 39.39% compared with two statically assigned backends. These results show that lifecycle coordination exploits inter-task timing slack for on-chip sharing, increasing service capacity under limited resources.
ER -