Simulations of MAPS designs for FCC-ee
Abstract
Future electron-positron colliders such as the future circular collider require vertex detectors with excellent spatial resolution and a low material budget. Monolithic active pixel sensors (MAPS) are a leading candidate technology because they integrate the sensing volume and readout electronics within a single thin silicon substrate and can operate at power densities compatible with air cooling. This paper presents the design and optimization of a high-voltage MAPS (HV-MAPS) pixel structure with a thickness of 25 μm and a pitch of 50 μm, developed using TCAD process and device simulations. The implantation energies and doses of the top-side implants are optimized with respect to the maximum electric field, sensor capacitance, and signals induced at each contact by minimum-ionizing particles. The optimized design reaches full depletion at a bias voltage of approximately -3 V and has an estimated breakdown voltage magnitude of 300-390 V. At a bias voltage of -100 V, the simulated charge-collection efficiency is approximately 90% outside the well regions and 80% within them and remains nearly independent of the angle of incidence.
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BibTeX
@misc{shekar2026simulations,
title = {{Simulations of MAPS designs for FCC-ee}},
author = {Danush Shekar and Doug Berry and Ron Lipton and Corrinne Mills},
howpublished = {arXiv},
year = {2026},
month = oct,
doi = {10.48550/arxiv.2610.28946},
eprint = {2610.28946},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2610.28946},
note = {CC BY 4.0},
}
RIS
TY - UNPB
TI - Simulations of MAPS designs for FCC-ee
AU - Danush Shekar
AU - Doug Berry
AU - Ron Lipton
AU - Corrinne Mills
PY - 2026
DA - 2026/10/20
PB - arXiv
DO - 10.48550/arxiv.2610.28946
UR - https://arxiv.org/abs/2610.28946
AB - Future electron-positron colliders such as the future circular collider require vertex detectors with excellent spatial resolution and a low material budget. Monolithic active pixel sensors (MAPS) are a leading candidate technology because they integrate the sensing volume and readout electronics within a single thin silicon substrate and can operate at power densities compatible with air cooling. This paper presents the design and optimization of a high-voltage MAPS (HV-MAPS) pixel structure with a thickness of 25 μm and a pitch of 50 μm, developed using TCAD process and device simulations. The implantation energies and doses of the top-side implants are optimized with respect to the maximum electric field, sensor capacitance, and signals induced at each contact by minimum-ionizing particles. The optimized design reaches full depletion at a bias voltage of approximately -3 V and has an estimated breakdown voltage magnitude of 300-390 V. At a bias voltage of -100 V, the simulated charge-collection efficiency is approximately 90% outside the well regions and 80% within them and remains nearly independent of the angle of incidence.
ER -