HybridQC: Hardware-Grounded Simulation of Tightly Integrated Hybrid Quantum-Classical Systems
Abstract
Hybrid quantum-classical performance depends on how quantum processors share classical compute, controllers, memory, and communication links. Circuit simulators and provider measurements expose kernel and job behavior, but leave topology-level questions about controller bottlenecks, quantum capacity, and mixed-workload contention unanswered. We present HybridQC, a discrete-event simulator for configurable hybrid compute units (HCUs). Users specify resource graphs containing classical compute, memory, controllers, quantum annealing (QA) and digital quantum computing (DQC) devices, and links. Jobs become dependent stages for preparation, quantum execution, transfers, reconstruction, and postprocessing. Finite capacities and selectable scheduling policies determine where stages wait and overlap. Service profiles use measurements from D-Wave Advantage 1 and Advantage 2 and IBM Kingston, Marrakesh, and Fez, separating physical quantum-processor occupancy from cloud wall time. Mean absolute percentage errors are 3.92%-8.04% for D-Wave access time and 5.26%-19.01% for IBM quantum seconds. Balanced 10x HCU scaling improves makespan by 2.19x-3.42x, while policy choice changes makespan by 1.80x for a mixed workload with 20 jobs per workload family. Scaling depends on which inputs grow: 100x data growth yields median runtime near 306 s, while 100x joint growth in circuits, shots, and depth reaches 4.806 x 10^7 s on the fixed HCU. HybridQC enables designers to study topology, scheduling, and workload growth before tightly integrated quantum-classical machines exist physically.
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BibTeX
@misc{christou2026hybridqc,
title = {{HybridQC: Hardware-Grounded Simulation of Tightly Integrated Hybrid Quantum-Classical Systems}},
author = {Panayiotis Christou and Shuwen Kan and Ying Mao},
howpublished = {arXiv},
year = {2026},
month = oct,
doi = {10.48550/arxiv.2607.13352},
eprint = {2607.13352},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2607.13352},
}
RIS
TY - UNPB
TI - HybridQC: Hardware-Grounded Simulation of Tightly Integrated Hybrid Quantum-Classical Systems
AU - Panayiotis Christou
AU - Shuwen Kan
AU - Ying Mao
PY - 2026
DA - 2026/10/17
PB - arXiv
DO - 10.48550/arxiv.2607.13352
UR - https://arxiv.org/abs/2607.13352
AB - Hybrid quantum-classical performance depends on how quantum processors share classical compute, controllers, memory, and communication links. Circuit simulators and provider measurements expose kernel and job behavior, but leave topology-level questions about controller bottlenecks, quantum capacity, and mixed-workload contention unanswered. We present HybridQC, a discrete-event simulator for configurable hybrid compute units (HCUs). Users specify resource graphs containing classical compute, memory, controllers, quantum annealing (QA) and digital quantum computing (DQC) devices, and links. Jobs become dependent stages for preparation, quantum execution, transfers, reconstruction, and postprocessing. Finite capacities and selectable scheduling policies determine where stages wait and overlap. Service profiles use measurements from D-Wave Advantage 1 and Advantage 2 and IBM Kingston, Marrakesh, and Fez, separating physical quantum-processor occupancy from cloud wall time. Mean absolute percentage errors are 3.92%-8.04% for D-Wave access time and 5.26%-19.01% for IBM quantum seconds. Balanced 10x HCU scaling improves makespan by 2.19x-3.42x, while policy choice changes makespan by 1.80x for a mixed workload with 20 jobs per workload family. Scaling depends on which inputs grow: 100x data growth yields median runtime near 306 s, while 100x joint growth in circuits, shots, and depth reaches 4.806 x 10^7 s on the fixed HCU. HybridQC enables designers to study topology, scheduling, and workload growth before tightly integrated quantum-classical machines exist physically.
ER -