Resolving the Thermal Labyrinth inside 3D-IC Stacks
Abstract
The heat pathways in 3D-ICs have long been a labyrinth lacking experimental investigations into spatial distribution of thermal properties, severely limiting study of internal thermal management inside chips. For the first time, we established a methodology for 3D thermal characterizations of advanced 3D-ICs, implemented through a systematic workflow that enables layer-resolved thermal property extraction and the construction of a location-specific thermal database. We demonstrated its application to an advanced sample featuring 2.2-μm-diameter TSVs and ~2-μm-pitch face-to-face hybrid bonding (HB). Time-domain and steady-state thermoreflectance were used to extract the thermal conductivities (TCs) of Al traces, TSV, BEOL interconnects and HB pads, indicating HB structure enables efficient thermal transport with 9 W/m-K TC. Further, we mapped and visualized the TC distribution of TSV structures and RDL Cu wires with small step sizes down to 0.2 μm. Utilizing these results, we proposed an experiment-based thermal model to reveal that co-evolution of interconnect and substrate TCs is essential for thermal design and fabrication towards effective cooling optimization.
Related
- Predictive Structure to Thermal Conductivity Modeling Framework for BEOL Interconnect Stacks in Advanced Technology Nodes Enabled by Extensive Layer Resolved Thermal Measurements
- Baryon-to-meson ratios in the Lund jet plane: resolving string-junction and thermal-fragmentation effects
- Orientational frustration drives enhanced diffusion of anisotropic particles in a liquid labyrinth
- GIT for root stacks and 3d mirror symmetry
- Intrinsic spin-orbit coupling in graphene stacks
BibTeX
@misc{guo2026resolving,
title = {{Resolving the Thermal Labyrinth inside 3D-IC Stacks}},
author = {Xufei Guo and Yiyun He and Zirou Chen and Zifeng Huang and Runsheng Wang and Zhe Cheng},
howpublished = {arXiv},
year = {2026},
month = oct,
doi = {10.48550/arxiv.2610.26647},
eprint = {2610.26647},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2610.26647},
}
RIS
TY - UNPB
TI - Resolving the Thermal Labyrinth inside 3D-IC Stacks
AU - Xufei Guo
AU - Yiyun He
AU - Zirou Chen
AU - Zifeng Huang
AU - Runsheng Wang
AU - Zhe Cheng
PY - 2026
DA - 2026/10/19
PB - arXiv
DO - 10.48550/arxiv.2610.26647
UR - https://arxiv.org/abs/2610.26647
AB - The heat pathways in 3D-ICs have long been a labyrinth lacking experimental investigations into spatial distribution of thermal properties, severely limiting study of internal thermal management inside chips. For the first time, we established a methodology for 3D thermal characterizations of advanced 3D-ICs, implemented through a systematic workflow that enables layer-resolved thermal property extraction and the construction of a location-specific thermal database. We demonstrated its application to an advanced sample featuring 2.2-μm-diameter TSVs and ~2-μm-pitch face-to-face hybrid bonding (HB). Time-domain and steady-state thermoreflectance were used to extract the thermal conductivities (TCs) of Al traces, TSV, BEOL interconnects and HB pads, indicating HB structure enables efficient thermal transport with 9 W/m-K TC. Further, we mapped and visualized the TC distribution of TSV structures and RDL Cu wires with small step sizes down to 0.2 μm. Utilizing these results, we proposed an experiment-based thermal model to reveal that co-evolution of interconnect and substrate TCs is essential for thermal design and fabrication towards effective cooling optimization.
ER -