Development of an FPGA-Based Readout System and Functional Characterization of a Custom NSX1 ASIC for X-ray instrumentation

@misc{poudyal2026development,
  title = {{Development of an FPGA-Based Readout System and Functional Characterization of a Custom NSX1 ASIC for X-ray instrumentation}},
  author = {Nabin Poudyal and Wayne Baumgartner and Sukanya Chakrabarti and Gianluigi De Geronimo and Wesley Hodge and Peter Jenke and Paul Ray and Jarred Roberts and Eric Wulf},
  howpublished = {arXiv},
  year = {2026},
  month = oct,
  doi = {10.48550/arxiv.2610.33759},
  eprint = {2610.33759},
  archivePrefix = {arXiv},
  url = {https://arxiv.org/abs/2610.33759},
}

TY  - UNPB
TI  - Development of an FPGA-Based Readout System and Functional Characterization of a Custom NSX1 ASIC for X-ray instrumentation
AU  - Nabin Poudyal
AU  - Wayne Baumgartner
AU  - Sukanya Chakrabarti
AU  - Gianluigi De Geronimo
AU  - Wesley Hodge
AU  - Peter Jenke
AU  - Paul Ray
AU  - Jarred Roberts
AU  - Eric Wulf
PY  - 2026
DA  - 2026/10/24
PB  - arXiv
DO  - 10.48550/arxiv.2610.33759
UR  - https://arxiv.org/abs/2610.33759
AB  - We developed an FPGA-based readout system for a front-end ASIC (NSX1) with 64 channels to read out a large- area silicon drift detector used in X-ray detection instruments such as the Wide Field Monitor module for the STROBE-X mission concept. The FPGA acts as a central controller for the NSX1 configuration, implementing trigger handling and event sequencing, precise event timestamping, control of an external ADC for digitization, and data transfer to the host PC. The system enables comprehensive ASIC characterization; here, we demonstrate preliminary ASIC functionality and characterization tests using a calibrated pulser for two programmable linear gain responses of 375 mV/fC and 750 mV/fC. These preliminary results validate the low-noise performance of the NSX1 ASIC and demonstrate successful integration of the DAQ system.
ER  -