Accurate gap control of 3D-integrated superconducting quantum circuits using asymmetric indium architecture and multi-angle flip-chip bonding
Abstract
Flip-chip 3D integration is a key enabling technology for overcoming the routing and layout constraints of planar superconducting quantum processors, but it requires accurate and uniform control of the inter-chip spacing while preserving qubit coherence. In conventional processes, thick indium bumps are deposited symmetrically on both chips, while dedicated spacers are introduced to limit the residual tilt. Here, we present a flip-chip bonding process based on an asymmetric indium architecture, combining 20 μm thick indium bumps on the control chip with 200 nm thin indium pads on the qubit chip. Using electrical and microwave measurements, we demonstrate low resistance and low loss indium interconnects, and show that transmon qubits integrated with this process reach relaxation and coherence times of T1=(159±14) μs and T2,echo=(294±42) μs, respectively, comparable to planar devices. Combined with a multi angle compression procedure that suppresses systematic tilt, this approach reduces the average post bonding tilt to (20±12) μrad. These results establish an asymmetric indium architecture combined with multi angle compression as a robust, coherence preserving route toward 3D-integrated superconducting quantum processors.
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BibTeX
@misc{richard2026accurate,
title = {{Accurate gap control of 3D-integrated superconducting quantum circuits using asymmetric indium architecture and multi-angle flip-chip bonding}},
author = {L. Richard and N. Bruckmoser and J. Feigl and D. Bunch and A. Bhattacharjee and L. Koch and I. Tsitsilin and V. P. Bader and H. Hu and L. Södergren and S. Filipp},
howpublished = {arXiv},
year = {2026},
month = oct,
doi = {10.48550/arxiv.2610.21435},
eprint = {2610.21435},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2610.21435},
}
RIS
TY - UNPB
TI - Accurate gap control of 3D-integrated superconducting quantum circuits using asymmetric indium architecture and multi-angle flip-chip bonding
AU - L. Richard
AU - N. Bruckmoser
AU - J. Feigl
AU - D. Bunch
AU - A. Bhattacharjee
AU - L. Koch
AU - I. Tsitsilin
AU - V. P. Bader
AU - H. Hu
AU - L. Södergren
AU - S. Filipp
PY - 2026
DA - 2026/10/16
PB - arXiv
DO - 10.48550/arxiv.2610.21435
UR - https://arxiv.org/abs/2610.21435
AB - Flip-chip 3D integration is a key enabling technology for overcoming the routing and layout constraints of planar superconducting quantum processors, but it requires accurate and uniform control of the inter-chip spacing while preserving qubit coherence. In conventional processes, thick indium bumps are deposited symmetrically on both chips, while dedicated spacers are introduced to limit the residual tilt. Here, we present a flip-chip bonding process based on an asymmetric indium architecture, combining 20 μm thick indium bumps on the control chip with 200 nm thin indium pads on the qubit chip. Using electrical and microwave measurements, we demonstrate low resistance and low loss indium interconnects, and show that transmon qubits integrated with this process reach relaxation and coherence times of T_1=(159±14) μs and T_2,echo=(294±42) μs, respectively, comparable to planar devices. Combined with a multi angle compression procedure that suppresses systematic tilt, this approach reduces the average post bonding tilt to (20±12) μrad. These results establish an asymmetric indium architecture combined with multi angle compression as a robust, coherence preserving route toward 3D-integrated superconducting quantum processors.
ER -