Real-time BP decoding of a high-rate QEC code
Abstract
We present a real-time FPGA decoder for a high-rate $[[512,174,8]]$ 3D product qLDPC code. We construct a circuit-level detector-error model for a compact syndrome-extraction schedule and propose a small parallel ensemble of row-wise serial min-sum decoders with cumulative memory. The decoder matches BP+OSD−CS10 accuracy with one core and Relay-BP accuracy with three cores. The FPGA implementation meets the latency budget of neutral-atom and trapped-ion systems. An ASIC implementation would improve the latency, enabling real time decoding even for superconducting systems. At a physical error rate of p=10−3, three FPGA devices decode 174 logical qubits with a logical error rate of 5×10−7 and effective distance 6. For p=10−4, and assuming the number of BP iterations is capped to 30, the decoder's average latency is 5.1\textmu s and its worst-case latency is 97.9\textmu s.
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BibTeX
@misc{kell2026realtime,
title = {{Real-time BP decoding of a high-rate QEC code}},
author = {Andreas Kell and Daniel Herr and Daniel Bascones García and Alexandru Paler and Davide Orsucci and Francisco Lázaro and Francisco García Herrero},
howpublished = {arXiv},
year = {2026},
month = oct,
doi = {10.48550/arxiv.2610.41413},
eprint = {2610.41413},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2610.41413},
}
RIS
TY - UNPB
TI - Real-time BP decoding of a high-rate QEC code
AU - Andreas Kell
AU - Daniel Herr
AU - Daniel Bascones García
AU - Alexandru Paler
AU - Davide Orsucci
AU - Francisco Lázaro
AU - Francisco García Herrero
PY - 2026
DA - 2026/10/30
PB - arXiv
DO - 10.48550/arxiv.2610.41413
UR - https://arxiv.org/abs/2610.41413
AB - We present a real-time FPGA decoder for a high-rate $[[512,174,8]]$ 3D product qLDPC code. We construct a circuit-level detector-error model for a compact syndrome-extraction schedule and propose a small parallel ensemble of row-wise serial min-sum decoders with cumulative memory. The decoder matches BP+OSD−CS_10 accuracy with one core and Relay-BP accuracy with three cores. The FPGA implementation meets the latency budget of neutral-atom and trapped-ion systems. An ASIC implementation would improve the latency, enabling real time decoding even for superconducting systems. At a physical error rate of p=10^−3, three FPGA devices decode 174 logical qubits with a logical error rate of 5×10^−7 and effective distance 6. For p=10^−4, and assuming the number of BP iterations is capped to 30, the decoder's average latency is 5.1\textmu s and its worst-case latency is 97.9\textmu s.
ER -