Skip to content
DraconiticResearch
Search Sources API
203,234 studies31 sourcesUpdated 12 min ago
PreprintCC BY 4.0arXiv

Error-Corrected Memory and Logic on a Heavy-Hex Superconducting-Qubit Processor

Abstract

Large quantum computations require high-fidelity error-corrected memory and fault-tolerant logical operations. To achieve these with superconducting circuits, quantum processors will need many components operating with low error rates. In practice, fabrication of monolithic superconducting devices produces unavoidable heterogeneity in component performance, which the quantum computer must accommodate. We implement strategies to operate a large dynamic compass code on an array of 156 superconducting qubits arranged on a heavy-hexagonal lattice, making use of the entire monolithic quantum processor and redesigning our measurement schedule to exclude underperforming components. We demonstrate improvements of up to 35% in logical error probabilities for a memory experiment by using a noise-informed decoder combined with strategies to exclude the worst-performing qubits and couplers, along with post-selecting on shots with a low probability of leakage errors. In addition to these memory results, we also observe performance gains of up to 56% when these strategies are applied to measurement-based logic, demonstrated by stability experiments. We furthermore demonstrate high-fidelity fault-tolerant logic through lattice surgery. Through pre-selection filtering techniques, we can obtain Bell fidelities above 77%, and further logical gap post-selection using exclusive decoding increases these fidelities to above 97%. Our experiments demonstrate that high performance can be maintained in key elements of fault-tolerant quantum memory and logic when working on monolithic superconducting quantum processors with underperforming components, by using a suite of noise-informed quantum error correction strategies.

Related

  1. Demonstration of Logical Error Suppression in a Surface Code Memory on a Cloud-Accessible IBM Superconducting Processor
    Shuwen Kan, Aaron Hoyt, Sean Garner +8
    arXivPreprintCC BY 4.0Full textQuantum physics & quantum informationarXiv
  2. Certifying bipartite entanglement on a superconducting processor from a corrected QAOA cost layer
    Carlos-Miguel Lorenzo
    arXivPreprintCC BY 4.0Full textQuantum physics & quantum informationarXiv
  3. Experimental Observation of Error-Resilience Phase Transition on Superconducting Quantum Processor
    Emanuel Dallas, Mario Morford-Oberst, Eric Weine
    arXivPreprintCC BY 4.0Full textQuantum physics & quantum informationarXiv
  4. Modular Neural Decoder for Surface Code Memory and Logic on Superconducting Processors
    Moritz Lange, Ole Fjeldså, Gustaf Jonasson Johansson +1
    arXivPreprintarXiv licenceFull textQuantum physics & quantum informationarXiv
  5. Observation and Modulation of the Quantum Mpemba Effect on a Superconducting Quantum Processor
    Yueshan Xu, Cai-Ping Fang, B. Chen +33
    Physical Review LettersPeer-reviewedLicence not statedFull text31 citedAtomic, molecular & optical physicsOpenAlex
BibTeX
@misc{mclauchlan2026errorcorrected,
  title = {{Error-Corrected Memory and Logic on a Heavy-Hex Superconducting-Qubit Processor}},
  author = {Campbell K. McLauchlan and Georgia M. Nixon and Julien M. Drouet and Xanda C. Kolesnikow and Seok-Hyung Lee and James Raftery and Karthik Siva and Stephen D. Bartlett and Benjamin J. Brown and Robin Harper},
  howpublished = {arXiv},
  year = {2026},
  month = oct,
  doi = {10.48550/arxiv.2610.11658},
  eprint = {2610.11658},
  archivePrefix = {arXiv},
  url = {https://arxiv.org/abs/2610.11658},
  note = {CC BY 4.0},
}
RIS
TY  - UNPB
TI  - Error-Corrected Memory and Logic on a Heavy-Hex Superconducting-Qubit Processor
AU  - Campbell K. McLauchlan
AU  - Georgia M. Nixon
AU  - Julien M. Drouet
AU  - Xanda C. Kolesnikow
AU  - Seok-Hyung Lee
AU  - James Raftery
AU  - Karthik Siva
AU  - Stephen D. Bartlett
AU  - Benjamin J. Brown
AU  - Robin Harper
PY  - 2026
DA  - 2026/10/08
PB  - arXiv
DO  - 10.48550/arxiv.2610.11658
UR  - https://arxiv.org/abs/2610.11658
AB  - Large quantum computations require high-fidelity error-corrected memory and fault-tolerant logical operations. To achieve these with superconducting circuits, quantum processors will need many components operating with low error rates. In practice, fabrication of monolithic superconducting devices produces unavoidable heterogeneity in component performance, which the quantum computer must accommodate. We implement strategies to operate a large dynamic compass code on an array of 156 superconducting qubits arranged on a heavy-hexagonal lattice, making use of the entire monolithic quantum processor and redesigning our measurement schedule to exclude underperforming components. We demonstrate improvements of up to 35% in logical error probabilities for a memory experiment by using a noise-informed decoder combined with strategies to exclude the worst-performing qubits and couplers, along with post-selecting on shots with a low probability of leakage errors. In addition to these memory results, we also observe performance gains of up to 56% when these strategies are applied to measurement-based logic, demonstrated by stability experiments. We furthermore demonstrate high-fidelity fault-tolerant logic through lattice surgery. Through pre-selection filtering techniques, we can obtain Bell fidelities above 77%, and further logical gap post-selection using exclusive decoding increases these fidelities to above 97%. Our experiments demonstrate that high performance can be maintained in key elements of fault-tolerant quantum memory and logic when working on monolithic superconducting quantum processors with underperforming components, by using a suite of noise-informed quantum error correction strategies.
ER  -