Mitigating Capacitive Loading Enables Fast Two-Qubit Gates in Highly Connected Fluxonium Quantum Processors
Abstract
Fluxonium qubits combine long coherence times with strong anharmonicity, making them attractive for scalable superconducting quantum processors. Recent experiments have demonstrated high-fidelity two-qubit gates and multi-qubit entanglement in one-dimensional and connectivity-four fluxonium processors, motivating their extension to highly connected two-dimensional (2D) architectures. A central challenge in this extension is to achieve strong coupling to multiple circuit elements while preserving the finite capacitance budget of fluxonium qubits, which constrains the attainable qubit-qubit effective coupling strength and, consequently, two-qubit gate performance. Here, we establish a unified theoretical framework that identifies the connectivity-dependent upper bound on capacitive coupling and quantifies its reduction by distinct parasitic-capacitance channels, applicable across both fluxonium and transmon regimes. We show that pad-to-ground loading is primarily geometry limited and can be substantially suppressed through qubit-pad engineering, whereas inter-pad loading is ultimately constrained by parasitic capacitances of Josephson junctions and Josephson junction arrays. Building on these insights, we formulate practical design principles and numerically demonstrate two-qubit gates as fast as 27 ns and leakage-induced infidelity below 10−3 under representative fabrication variations in 2D fluxonium architectures. These results establish a quantitative framework for understanding and mitigating capacitive loading, suggesting that it does not impose a fundamental performance limit on highly connected fluxonium processors.
Related
- Optimal Control of a Fluxonium Circuit with the Q-PRONTO Numerical Method
- Bosonic quantum control with a weakly coupled fluxonium qubit
- Numerical Modeling of Quasiparticle-Induced Dissipation in Fluxonium Qubits
- Bosonic Error Correction with Fluxonium
- Fast CZ gate in hybrid fluxonium-transmon systems with tunable couplers
BibTeX
@misc{guan2026mitigating,
title = {{Mitigating Capacitive Loading Enables Fast Two-Qubit Gates in Highly Connected Fluxonium Quantum Processors}},
author = {Quan Guan and Guo Xuan Chan and Xu Dou and Chunqing Deng and Lijing Jin},
howpublished = {arXiv},
year = {2026},
month = sep,
doi = {10.48550/arxiv.2607.22138},
eprint = {2607.22138},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2607.22138},
}
RIS
TY - UNPB
TI - Mitigating Capacitive Loading Enables Fast Two-Qubit Gates in Highly Connected Fluxonium Quantum Processors
AU - Quan Guan
AU - Guo Xuan Chan
AU - Xu Dou
AU - Chunqing Deng
AU - Lijing Jin
PY - 2026
DA - 2026/09/03
PB - arXiv
DO - 10.48550/arxiv.2607.22138
UR - https://arxiv.org/abs/2607.22138
AB - Fluxonium qubits combine long coherence times with strong anharmonicity, making them attractive for scalable superconducting quantum processors. Recent experiments have demonstrated high-fidelity two-qubit gates and multi-qubit entanglement in one-dimensional and connectivity-four fluxonium processors, motivating their extension to highly connected two-dimensional (2D) architectures. A central challenge in this extension is to achieve strong coupling to multiple circuit elements while preserving the finite capacitance budget of fluxonium qubits, which constrains the attainable qubit-qubit effective coupling strength and, consequently, two-qubit gate performance. Here, we establish a unified theoretical framework that identifies the connectivity-dependent upper bound on capacitive coupling and quantifies its reduction by distinct parasitic-capacitance channels, applicable across both fluxonium and transmon regimes. We show that pad-to-ground loading is primarily geometry limited and can be substantially suppressed through qubit-pad engineering, whereas inter-pad loading is ultimately constrained by parasitic capacitances of Josephson junctions and Josephson junction arrays. Building on these insights, we formulate practical design principles and numerically demonstrate two-qubit gates as fast as 27 ns and leakage-induced infidelity below 10^−3 under representative fabrication variations in 2D fluxonium architectures. These results establish a quantitative framework for understanding and mitigating capacitive loading, suggesting that it does not impose a fundamental performance limit on highly connected fluxonium processors.
ER -