Hierarchical Quantum Logical Processor with Amortized Long-Range Connectivity
Abstract
High qubit overhead is a key bottleneck for fault-tolerant quantum computation. Quantum low-density parity-check (qLDPC) codes offer high encoding efficiency but typically require non-local connectivity in every syndrome extraction cycle, incurring additional physical errors and implementation complexity. We introduce a hierarchical logical processor (HLP) architecture that implements a high-rate quantum CSS code with distance-d0 rotated surface codes (RSC), allowing long-range connectivity to be used only once every Θ(d0) rounds of surface-code syndrome extraction. HLPs introduce elongated RSC patches called shuttle buses. Using transversal hybrid-unit CNOT gates, a single shuttle bus can simultaneously couple to multiple standard RSC patches. This capability enables efficient level-1 syndrome extraction with suppressed level-1 error correlations and supports highly parallel logical Pauli measurements. We perform circuit-level simulations of several concrete HLP constructions and benchmark both logical memory and logical Pauli measurement performance. At a physical error rate of 10−3, a hierarchical logical processor can achieve 3-4 times higher qubit efficiency than the rotated surface code and 20-30 times shorter logical error-correction cycle times than the yoked surface code.
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BibTeX
@misc{chen2026hierarchical,
title = {{Hierarchical Quantum Logical Processor with Amortized Long-Range Connectivity}},
author = {Zi-Han Chen and Ming-Cheng Chen and Chao-Yang Lu and Jian-Wei Pan},
howpublished = {arXiv},
year = {2026},
month = oct,
doi = {10.48550/arxiv.2606.22594},
eprint = {2606.22594},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2606.22594},
}
RIS
TY - UNPB
TI - Hierarchical Quantum Logical Processor with Amortized Long-Range Connectivity
AU - Zi-Han Chen
AU - Ming-Cheng Chen
AU - Chao-Yang Lu
AU - Jian-Wei Pan
PY - 2026
DA - 2026/10/01
PB - arXiv
DO - 10.48550/arxiv.2606.22594
UR - https://arxiv.org/abs/2606.22594
AB - High qubit overhead is a key bottleneck for fault-tolerant quantum computation. Quantum low-density parity-check (qLDPC) codes offer high encoding efficiency but typically require non-local connectivity in every syndrome extraction cycle, incurring additional physical errors and implementation complexity. We introduce a hierarchical logical processor (HLP) architecture that implements a high-rate quantum CSS code with distance-d_0 rotated surface codes (RSC), allowing long-range connectivity to be used only once every Θ(d_0) rounds of surface-code syndrome extraction. HLPs introduce elongated RSC patches called shuttle buses. Using transversal hybrid-unit CNOT gates, a single shuttle bus can simultaneously couple to multiple standard RSC patches. This capability enables efficient level-1 syndrome extraction with suppressed level-1 error correlations and supports highly parallel logical Pauli measurements. We perform circuit-level simulations of several concrete HLP constructions and benchmark both logical memory and logical Pauli measurement performance. At a physical error rate of 10^−3, a hierarchical logical processor can achieve 3-4 times higher qubit efficiency than the rotated surface code and 20-30 times shorter logical error-correction cycle times than the yoked surface code.
ER -