Phase-Altered Interleaved Randomized Benchmarking for Compiled Non-Clifford Gates
Abstract
Interleaved randomized benchmarking (IRB) provides a scalable estimate of a gate's error rate, but its standard guarantees require the interleaved gate to be Clifford~\cite{Magesan2012Interleaved,magesan2012characterizing}. In superconducting processors, many non-Clifford phase gates in compiled circuits are implemented virtually as software-defined frame updates rather than as additional control pulses~\cite{mckay2017efficient}. This raises the question of whether inserting or removing such virtual phases measurably changes IRB error estimates. We introduce \emph{phase-altered interleaved randomized benchmarking} (PA-IRB), a paired-IRB diagnostic protocol comparing phase-stripped and phase-dressed Clifford interleaving gates derived from the same compiled implementation. PA-IRB reports Δr=rd−rs with combined uncertainty to test whether virtual phase gates affect the extracted IRB decay beyond statistical error. As a case study, we apply PA-IRB to a compiled Toffoli gate executed on IBM superconducting processors, where the constituent T/T† gates are implemented as virtual Z rotations. Across tested calibration runs, Δr is consistent with zero within uncertainty, indicating that virtual phase addition or removal does not measurably alter the IRB-derived error estimate under the employed compilation and execution stack. More generally, PA-IRB provides a lightweight, abstraction-aware diagnostic for benchmarking workflows involving software-defined phase operations. The same paired comparison can also be used to place operational bounds on the contribution of non-Clifford components to the compiled gate error, even when those components are physically executed rather than implemented virtually.
Related
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BibTeX
@misc{grigorova2026phasealtered,
title = {{Phase-Altered Interleaved Randomized Benchmarking for Compiled Non-Clifford Gates}},
author = {Simona K. Grigorova and Nikolay V. Vitanov and Boyan T. Torosov},
howpublished = {arXiv},
year = {2026},
month = oct,
doi = {10.48550/arxiv.2606.30327},
eprint = {2606.30327},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2606.30327},
}
RIS
TY - UNPB
TI - Phase-Altered Interleaved Randomized Benchmarking for Compiled Non-Clifford Gates
AU - Simona K. Grigorova
AU - Nikolay V. Vitanov
AU - Boyan T. Torosov
PY - 2026
DA - 2026/10/01
PB - arXiv
DO - 10.48550/arxiv.2606.30327
UR - https://arxiv.org/abs/2606.30327
AB - Interleaved randomized benchmarking (IRB) provides a scalable estimate of a gate's error rate, but its standard guarantees require the interleaved gate to be Clifford~\cite{Magesan2012Interleaved,magesan2012characterizing}. In superconducting processors, many non-Clifford phase gates in compiled circuits are implemented virtually as software-defined frame updates rather than as additional control pulses~\cite{mckay2017efficient}. This raises the question of whether inserting or removing such virtual phases measurably changes IRB error estimates. We introduce \emph{phase-altered interleaved randomized benchmarking} (PA-IRB), a paired-IRB diagnostic protocol comparing phase-stripped and phase-dressed Clifford interleaving gates derived from the same compiled implementation. PA-IRB reports Δr=r_d−r_s with combined uncertainty to test whether virtual phase gates affect the extracted IRB decay beyond statistical error. As a case study, we apply PA-IRB to a compiled Toffoli gate executed on IBM superconducting processors, where the constituent T/T^† gates are implemented as virtual Z rotations. Across tested calibration runs, Δr is consistent with zero within uncertainty, indicating that virtual phase addition or removal does not measurably alter the IRB-derived error estimate under the employed compilation and execution stack. More generally, PA-IRB provides a lightweight, abstraction-aware diagnostic for benchmarking workflows involving software-defined phase operations. The same paired comparison can also be used to place operational bounds on the contribution of non-Clifford components to the compiled gate error, even when those components are physically executed rather than implemented virtually.
ER -