ReSNNance: an HDL generation framework for spiking neural networks
- 1Information Processing and Telecommunications Center, Escuela Técnica Superior de Ingenieros de Telecomunicación, Universidad Politécnica de Madrid
- 2Universidad Politécnica de Madrid - Indra
Abstract
Spiking neural networks (SNNs) are a promising computational paradigm for resource- and energy-constrained edge applications. However, their implementation on field-programmable gate arrays (FPGAs) remains a complex task that typically requires both neuromorphic-computing knowledge and hardware-description expertise. This work presents ReSNNance, an open-source framework for the automatic generation of synthesizable VHDL implementations from high-level software descriptions of SNNs. ReSNNance provides a Python-based workflow in which users define the network architecture, neuron parameters, numerical precision and target configuration, while the framework generates the corresponding hardware modules, parameter files and interconnections. Its modular architecture supports sequential networks composed of Dense, Conv2D and pooling layers based on fixed-point leaky integrate-and-fire neurons. The generated VHDL is intended to remain readable and configurable, allowing users to inspect, modify and integrate the resulting circuits into larger hardware designs. ReSNNance also supports design-space exploration through configurable numerical formats and network parameters, facilitating the evaluation of trade-offs between classification accuracy, resource utilization and performance. The complete workflow was demonstrated using a large fully connected network and a spiking LeNet-5 architecture for MNIST classification. Both networks were automatically translated into VHDL, verified against their software counterparts and implemented on an AMD Zynq UltraScale+ FPGA. The results show that ReSNNance provides a practical path from software-defined SNN models to functional FPGA implementations by automating the generation of the corresponding VHDL modules and network interconnections.
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BibTeX
@article{lopezasuncion2026resnnance,
title = {{ReSNNance: an HDL generation framework for spiking neural networks}},
author = {Samuel López-Asunción and Cristina Bermúdez-Martín and Pablo Ituero and Marisa Lopez-Vallejo},
journal = {Frontiers in Neuroscience},
year = {2026},
month = oct,
doi = {10.3389/fnins.2026.1958451},
url = {https://www.frontiersin.org/articles/10.3389/fnins.2026.1958451/full},
note = {CC BY 4.0},
}
RIS
TY - JOUR
TI - ReSNNance: an HDL generation framework for spiking neural networks
AU - Samuel López-Asunción
AU - Cristina Bermúdez-Martín
AU - Pablo Ituero
AU - Marisa Lopez-Vallejo
PY - 2026
DA - 2026/10/13
JO - Frontiers in Neuroscience
DO - 10.3389/fnins.2026.1958451
UR - https://www.frontiersin.org/articles/10.3389/fnins.2026.1958451/full
AB - Spiking neural networks (SNNs) are a promising computational paradigm for resource- and energy-constrained edge applications. However, their implementation on field-programmable gate arrays (FPGAs) remains a complex task that typically requires both neuromorphic-computing knowledge and hardware-description expertise. This work presents ReSNNance, an open-source framework for the automatic generation of synthesizable VHDL implementations from high-level software descriptions of SNNs. ReSNNance provides a Python-based workflow in which users define the network architecture, neuron parameters, numerical precision and target configuration, while the framework generates the corresponding hardware modules, parameter files and interconnections. Its modular architecture supports sequential networks composed of Dense, Conv2D and pooling layers based on fixed-point leaky integrate-and-fire neurons. The generated VHDL is intended to remain readable and configurable, allowing users to inspect, modify and integrate the resulting circuits into larger hardware designs. ReSNNance also supports design-space exploration through configurable numerical formats and network parameters, facilitating the evaluation of trade-offs between classification accuracy, resource utilization and performance. The complete workflow was demonstrated using a large fully connected network and a spiking LeNet-5 architecture for MNIST classification. Both networks were automatically translated into VHDL, verified against their software counterparts and implemented on an AMD Zynq UltraScale+ FPGA. The results show that ReSNNance provides a practical path from software-defined SNN models to functional FPGA implementations by automating the generation of the corresponding VHDL modules and network interconnections.
SN - 1662-453X
SN - 1662-4548
ER -