Fabrication And Characterization Of High-Quality Nb/Al-AlOx/Nb Cross-Type Josephson Tunnel Junctions Utilising CMP-based Planarisation Techniques
Abstract
Josephson tunnel junctions (JJs) are the fundamental building blocks of today's most advanced superconducting electronic components, such as qubits and superconducting quantum interference devices (SQUIDs). Given the ongoing demand for scalability of these devices on the wafer-scale, it is crucial to control the fabrication process as precisely as possible to ensure uniform quality and reproducibility. Today, window-type JJs are often used in the production of DC SQUIDs and while they are reliable and reproducible, they suffer from alignment inaccuracies caused by photolithography and unavoidable parasitic capacitances, thus limiting the energy sensitivity of DC SQUIDs. These problems can be circumvented by producing JJs with cross-type geometry, which allows for smaller junction areas and eliminates parasitic capacitances. Here we discuss the fabrication of Nb/Al-AlOx/Nb-based cross-type JJs, where the trilayer is embedded in sputter-deposited SiO2 to allow for planarisation of the structures and to ensure the reliable insulation of the sidewalls of the bottom electrode. Instead of lift-off processes that require a lot of time and potentially leave unwanted wings along the edges of microstructures behind that might compromise subsequent layers, we use chemical-mechanical polishing (CMP) for the removal of excess SiO2. This is not only much faster, but produces smooth and uniform surfaces, which in turn effectively improves the reliability of our JJ production process resulting in a high yield of over 90 % on wafer-scale. In addition, we discuss the influence of fabrication details on the quality and electrical properties of our JJs with different junction areas down to 1 μm × 1 μm distributed across the wafer and extract the junction specific quality parameters from their IV-characteristics and their Fraunhofer patterns.
Related
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- Finite-Temperature Transconductance of Multiterminal Josephson Junctions with Topological Andreev Spectra
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BibTeX
@misc{stoll2026fabrication,
title = {{Fabrication And Characterization Of High-Quality Nb/Al-AlO$_x$/Nb Cross-Type Josephson Tunnel Junctions Utilising CMP-based Planarisation Techniques}},
author = {Alexander Stoll and Andreas Reifenberger and Daniel Hengstler and Andreas Fleischmann and Christian Enss},
howpublished = {arXiv},
year = {2026},
month = sep,
doi = {10.48550/arxiv.2609.08569},
eprint = {2609.08569},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2609.08569},
}
RIS
TY - UNPB
TI - Fabrication And Characterization Of High-Quality Nb/Al-AlO_x/Nb Cross-Type Josephson Tunnel Junctions Utilising CMP-based Planarisation Techniques
AU - Alexander Stoll
AU - Andreas Reifenberger
AU - Daniel Hengstler
AU - Andreas Fleischmann
AU - Christian Enss
PY - 2026
DA - 2026/09/08
PB - arXiv
DO - 10.48550/arxiv.2609.08569
UR - https://arxiv.org/abs/2609.08569
AB - Josephson tunnel junctions (JJs) are the fundamental building blocks of today's most advanced superconducting electronic components, such as qubits and superconducting quantum interference devices (SQUIDs). Given the ongoing demand for scalability of these devices on the wafer-scale, it is crucial to control the fabrication process as precisely as possible to ensure uniform quality and reproducibility. Today, window-type JJs are often used in the production of DC SQUIDs and while they are reliable and reproducible, they suffer from alignment inaccuracies caused by photolithography and unavoidable parasitic capacitances, thus limiting the energy sensitivity of DC SQUIDs. These problems can be circumvented by producing JJs with cross-type geometry, which allows for smaller junction areas and eliminates parasitic capacitances. Here we discuss the fabrication of Nb/Al-AlOx/Nb-based cross-type JJs, where the trilayer is embedded in sputter-deposited SiO_2 to allow for planarisation of the structures and to ensure the reliable insulation of the sidewalls of the bottom electrode. Instead of lift-off processes that require a lot of time and potentially leave unwanted wings along the edges of microstructures behind that might compromise subsequent layers, we use chemical-mechanical polishing (CMP) for the removal of excess SiO_2. This is not only much faster, but produces smooth and uniform surfaces, which in turn effectively improves the reliability of our JJ production process resulting in a high yield of over 90 % on wafer-scale. In addition, we discuss the influence of fabrication details on the quality and electrical properties of our JJs with different junction areas down to 1 μm × 1 μm distributed across the wafer and extract the junction specific quality parameters from their IV-characteristics and their Fraunhofer patterns.
ER -