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Peer-reviewedCC BYACS nano

Graphene Field-Effect Transistor Process and Analysis Optimization in 200 mm Pilot-Line Environment.

  • Anton Murros1
  • Miika Soikkeli1
  • Anni Virta1
  • Arantxa Maestre2,3
  • Leire Morillo2
  • Alba Centeno2
  • Amaia Zurutuza2
  • Olli-Pekka Kilpi1
  1. 1VTT Technical Research Centre of Finland Ltd , P.O. Box 1000, EspooFI-02044 VTT, Finland.
  2. 2Graphenea S.A. , Paseo Mikeletegi 83, San Sebastian20009, Spain.
  3. 3ASM International, Kapeldreef 75, Leuven3001, Belgium.
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Abstract

The maturity of the chemical vapor deposition graphene-based device processing has increased from chip-level demonstrations to wafer-scale fabrication in the past few years. Due to this, wafer-scale electrical characterization and analysis of the fabricated devices have become increasingly important to enable extraction of multiple parameters with a minimal number of measurements for the quality-control purposes critical for industrial uptake of 2D material-based devices. As a crucial step, we demonstrate optimization of complementary metal-oxide semiconductor (CMOS) back-end-of-line (BEOL)-compatible graphene field-effect transistor (GFET) fabrication and analysis, including the gate stack, bottom contact, graphene patterning, and encapsulation process steps. The analysis methods include atomic force microscopy, scanning electron microscopy, and, most importantly, electrical characterization. The electrical characterization focuses on comparing different test structures and extraction methods for mobility, contact resistance, transfer curve hysteresis, and doping parameters. The comparison shows that the selected measurement test structures and analysis methods can have a large impact on the extracted values and should thus be considered when comparing data sets from different sources. The analysis shows that the optimized process offers a high device yield of 97% with good doping uniformity, contact resistance, and mobility as well as low transfer-curve hysteresis values on 200 mm wafers.

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Cite

BibTeXRIS
BibTeX
@article{murros2026graphene,
  title = {{Graphene Field-Effect Transistor Process and Analysis Optimization in 200 mm Pilot-Line Environment.}},
  author = {Anton Murros and Miika Soikkeli and Anni Virta and Arantxa Maestre and Leire Morillo and Alba Centeno and Amaia Zurutuza and Olli-Pekka Kilpi},
  journal = {ACS nano},
  year = {2026},
  month = sep,
  doi = {10.1021/acsnano.6c03282},
  url = {https://europepmc.org/article/MED/42916093},
  note = {CC BY},
}
RIS
TY  - JOUR
TI  - Graphene Field-Effect Transistor Process and Analysis Optimization in 200 mm Pilot-Line Environment.
AU  - Anton Murros
AU  - Miika Soikkeli
AU  - Anni Virta
AU  - Arantxa Maestre
AU  - Leire Morillo
AU  - Alba Centeno
AU  - Amaia Zurutuza
AU  - Olli-Pekka Kilpi
PY  - 2026
DA  - 2026/09/01
JO  - ACS nano
DO  - 10.1021/acsnano.6c03282
UR  - https://europepmc.org/article/MED/42916093
AB  - The maturity of the chemical vapor deposition graphene-based device processing has increased from chip-level demonstrations to wafer-scale fabrication in the past few years. Due to this, wafer-scale electrical characterization and analysis of the fabricated devices have become increasingly important to enable extraction of multiple parameters with a minimal number of measurements for the quality-control purposes critical for industrial uptake of 2D material-based devices. As a crucial step, we demonstrate optimization of complementary metal-oxide semiconductor (CMOS) back-end-of-line (BEOL)-compatible graphene field-effect transistor (GFET) fabrication and analysis, including the gate stack, bottom contact, graphene patterning, and encapsulation process steps. The analysis methods include atomic force microscopy, scanning electron microscopy, and, most importantly, electrical characterization. The electrical characterization focuses on comparing different test structures and extraction methods for mobility, contact resistance, transfer curve hysteresis, and doping parameters. The comparison shows that the selected measurement test structures and analysis methods can have a large impact on the extracted values and should thus be considered when comparing data sets from different sources. The analysis shows that the optimized process offers a high device yield of 97% with good doping uniformity, contact resistance, and mobility as well as low transfer-curve hysteresis values on 200 mm wafers.
SN  - 1936-0851
SN  - 1936-086X
ER  -