PreprintCC BY 4.0arXiv
A Scalable Two-Stage Back-End Architecture for 400GbE Data Acquisition Systems
Abstract
A primary challenge in High Energy Physics (HEP) data acquisition is the aggregation of numerous low-speed (10 Gb/s) radiation-hard data links into high-speed back-end interfaces. While high-end FPGAs traditionally perform this task, transceiver density and speed in modern devices can limit cost-effective scaling. This study proposes a two-stage architecture that utilizes mid-range FPGAs for decoding and Ethernet conversion, followed by a Microchip META-DX2+ Ethernet PHY that aggregates these streams into a 400 GbE interface. This study evaluates the design's performance, validating it as a scalable and cost-effective architecture for next-generation HEP data acquisition systems.
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BibTeX
@misc{perro2026scalable,
title = {{A Scalable Two-Stage Back-End Architecture for 400GbE Data Acquisition Systems}},
author = {Alberto Perro and Paolo Durante and Tommaso Colombo},
howpublished = {arXiv},
year = {2026},
month = nov,
doi = {10.48550/arxiv.2611.00116},
eprint = {2611.00116},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2611.00116},
note = {CC BY 4.0},
}
RIS
TY - UNPB
TI - A Scalable Two-Stage Back-End Architecture for 400GbE Data Acquisition Systems
AU - Alberto Perro
AU - Paolo Durante
AU - Tommaso Colombo
PY - 2026
DA - 2026/11/01
PB - arXiv
DO - 10.48550/arxiv.2611.00116
UR - https://arxiv.org/abs/2611.00116
AB - A primary challenge in High Energy Physics (HEP) data acquisition is the aggregation of numerous low-speed (10 Gb/s) radiation-hard data links into high-speed back-end interfaces. While high-end FPGAs traditionally perform this task, transceiver density and speed in modern devices can limit cost-effective scaling. This study proposes a two-stage architecture that utilizes mid-range FPGAs for decoding and Ethernet conversion, followed by a Microchip META-DX2+ Ethernet PHY that aggregates these streams into a 400 GbE interface. This study evaluates the design's performance, validating it as a scalable and cost-effective architecture for next-generation HEP data acquisition systems.
ER -