Weight-four parity checks in a spin-shuttling architecture
- 1QuTech and Kavli Institute of Nanoscience, Delft University of Technology, Delft, The Netherlands
- 2Netherlands Organization for Applied Scientific Research (TNO), Delft, The Netherlands
- 3QuTech and Kavli Institute of Nanoscience, Delft University of Technology, Delft, The Netherlands. [email protected]
Abstract
Recent advances in coherent spin shuttling have made sparse semiconductor spin-qubit arrays an appealing solid-state platform to realize quantum processors 1–7 . The dynamic and long-range connectivity enabled by shuttling is also essential for many quantum error-correction schemes 8–10 . Here we demonstrate a silicon spin-qubit device comprising a shuttling bus for coherently transporting qubits that can interact at four isolated locations that we call bus stops. We dynamically populate the array and tune all single- and two-qubit operations using shuttling and quantum non-demolition spin measurements, without access to charge sensing in most of the device. We achieve universal control of the effective five-qubit processor and select the connectivity required to form a surface-code stabilizer plaquette that supports X - and Z -type parity checks up to weight four. We use the parity checks to generate multi-qubit entanglement between all qubit combinations in the array and report the genuine entanglement of a five-qubit Greenberger–Horne–Zeilinger state, constituting one of the largest such states constructed with gate-defined semiconductor spins. The protocols developed here lay the groundwork for modular calibration and operation of sparse spin-qubit arrays, and we highlight the feasibility of near-term quantum error-correction experiments with mobile spin qubits.
Related
- Performance of the spin qubit shuttling architecture for a surface code implementation
- Quantum bivariate bicycle codes with weight-8 checks surpassing the BB benchmark
- Odd-parity magnon spin polarization from chiral four-spin exchange in a honeycomb antiferromagnet
- Shuttling-aware dynamical decoupling for quantum charge-coupled devices
- Parallel algebraic surgery for qLDPC codes with constant shuttling depth
BibTeX
@article{undseth2026weightfour,
title = {{Weight-four parity checks in a spin-shuttling architecture}},
author = {Brennan Undseth and Nicola Meggiato and Yi-Hsien Wu and Sam R. Katiraee-Far and Larysa Tryputen and Sander L. de Snoo and Davide Degli Esposti and Giordano Scappucci and Eliška Greplová and Lieven M. K. Vandersypen},
journal = {Nature},
year = {2026},
month = jul,
doi = {10.1038/s41586-026-10766-3},
url = {https://doi.org/10.1038/s41586-026-10766-3},
note = {CC BY},
}
RIS
TY - JOUR
TI - Weight-four parity checks in a spin-shuttling architecture
AU - Brennan Undseth
AU - Nicola Meggiato
AU - Yi-Hsien Wu
AU - Sam R. Katiraee-Far
AU - Larysa Tryputen
AU - Sander L. de Snoo
AU - Davide Degli Esposti
AU - Giordano Scappucci
AU - Eliška Greplová
AU - Lieven M. K. Vandersypen
PY - 2026
DA - 2026/07/29
JO - Nature
DO - 10.1038/s41586-026-10766-3
UR - https://doi.org/10.1038/s41586-026-10766-3
AB - Recent advances in coherent spin shuttling have made sparse semiconductor spin-qubit arrays an appealing solid-state platform to realize quantum processors 1–7 . The dynamic and long-range connectivity enabled by shuttling is also essential for many quantum error-correction schemes 8–10 . Here we demonstrate a silicon spin-qubit device comprising a shuttling bus for coherently transporting qubits that can interact at four isolated locations that we call bus stops. We dynamically populate the array and tune all single- and two-qubit operations using shuttling and quantum non-demolition spin measurements, without access to charge sensing in most of the device. We achieve universal control of the effective five-qubit processor and select the connectivity required to form a surface-code stabilizer plaquette that supports X - and Z -type parity checks up to weight four. We use the parity checks to generate multi-qubit entanglement between all qubit combinations in the array and report the genuine entanglement of a five-qubit Greenberger–Horne–Zeilinger state, constituting one of the largest such states constructed with gate-defined semiconductor spins. The protocols developed here lay the groundwork for modular calibration and operation of sparse spin-qubit arrays, and we highlight the feasibility of near-term quantum error-correction experiments with mobile spin qubits.
SN - 0028-0836
SN - 1476-4687
ER -