VERITAS 2.3.1: Optimisation and Characterisation of the Enhanced Readout ASIC for the NewAthena Wide Field Imager
Abstract
VERITAS 2.3.1 is the next iteration of the VErsatile Readout based on Integrated Trapezoidal Analogue Shapers (VERITAS) integrated circuit (IC) architecture for high-speed, low-noise readout of DEPleted Field Effect Transistor (DEPFET) detectors in the Wide Field Imager (WFI) on ESA's NewAthena X-ray satellite. Building on VERITAS 2.3, which demonstrated a short processing time of 2.5 us per readout and a system noise target of about 3 e- ENC RMS, the VERITAS 2.3.1 revision has been improved with additional features and targeted optimisations of existing analogue and digital blocks, alongside refined layout routing to reduce parasitic effects, to improve transient behavior, cross talk, manufacturability, and reliability while preserving the proven VERITAS architecture. The functionality and performance of VERITAS 2.3.1 was characterised in two steps. First by using a dedicated application specific integrated circuit (ASIC) only test setup. Second, a full scale module test setup is used, with integrated DEPFET sensors and readout electronics, under vacuum and at mission like temperatures. This paper presents the design updates and implementation details of the VERITAS 2.3.1, compares its measured performance to that of VERITAS 2.3, and discusses the impact of the added features, block-level optimisations, and routing improvements on overall system performance.
Versions
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BibTeX
@misc{dakshinamurthy2026veritas,
title = {{VERITAS 2.3.1: Optimisation and Characterisation of the Enhanced Readout ASIC for the NewAthena Wide Field Imager}},
author = {Ajay Kumar Dakshinamurthy and Sven Herrmann and Peter Orel and Anna-Katharina Schweingruber and Astrid Mayr and Johannes Muller-Seidlitz and Jonas Reiffers and Sebastian Albrecht and Steven W. Allen and Glenn Morris},
howpublished = {arXiv},
year = {2026},
month = aug,
doi = {10.48550/arxiv.2608.18880},
eprint = {2608.18880},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2608.18880},
note = {CC BY-NC-ND 4.0},
}
RIS
TY - UNPB
TI - VERITAS 2.3.1: Optimisation and Characterisation of the Enhanced Readout ASIC for the NewAthena Wide Field Imager
AU - Ajay Kumar Dakshinamurthy
AU - Sven Herrmann
AU - Peter Orel
AU - Anna-Katharina Schweingruber
AU - Astrid Mayr
AU - Johannes Muller-Seidlitz
AU - Jonas Reiffers
AU - Sebastian Albrecht
AU - Steven W. Allen
AU - Glenn Morris
PY - 2026
DA - 2026/08/19
PB - arXiv
DO - 10.48550/arxiv.2608.18880
UR - https://arxiv.org/abs/2608.18880
AB - VERITAS 2.3.1 is the next iteration of the VErsatile Readout based on Integrated Trapezoidal Analogue Shapers (VERITAS) integrated circuit (IC) architecture for high-speed, low-noise readout of DEPleted Field Effect Transistor (DEPFET) detectors in the Wide Field Imager (WFI) on ESA's NewAthena X-ray satellite. Building on VERITAS 2.3, which demonstrated a short processing time of 2.5 us per readout and a system noise target of about 3 e- ENC RMS, the VERITAS 2.3.1 revision has been improved with additional features and targeted optimisations of existing analogue and digital blocks, alongside refined layout routing to reduce parasitic effects, to improve transient behavior, cross talk, manufacturability, and reliability while preserving the proven VERITAS architecture. The functionality and performance of VERITAS 2.3.1 was characterised in two steps. First by using a dedicated application specific integrated circuit (ASIC) only test setup. Second, a full scale module test setup is used, with integrated DEPFET sensors and readout electronics, under vacuum and at mission like temperatures. This paper presents the design updates and implementation details of the VERITAS 2.3.1, compares its measured performance to that of VERITAS 2.3, and discusses the impact of the added features, block-level optimisations, and routing improvements on overall system performance.
ER -