FPGA-based muon shower identification and graph neural network tracking algorithms for HL-LHC triggers
Abstract
This work presents two hardware-accelerated strategies for the upgrade of the CMS Level-1 Trigger (L1T) to target efficiency losses due to highly energetic radiating muons and unconventional physics signatures, such as Long-Lived Particles (LLPs). Operating directly on low-level detector hits, the first strategy implements a dedicated muon shower identification algorithm in the CMS barrel region that monitors hit multiplicities in the Drift Tube chambers to generate Shower Primitives. Executing with sub-bunch-crossing latency and ultra-low resource consumption, this algorithm successfully tags showered muons and provides essential context for downstream track finders. The second approach targets the barrel-endcap transition (overlap) region by evaluating Graph Neural Networks to reconstruct displaced muon tracks. Following a divided methodology that first isolates hardware feasibility from evolving physics refinements, an initial proxy model based on a GraphSAGE architecture is evaluated to validate its viability on FPGAs within strict latency limits. This implementation utilizes an INT8-PO2 quantization technique coupled with a data-driven bit-width optimization. By replacing DSP-heavy fixed-point multiplications with fast compile-time arithmetic bit-shifts and allocating the minimum required bits per signal, this hardware-software co-design reduces DSP utilization to 20% and achieves a deterministic inference latency of just $19$ clock cycles. Together, these developments pave the way for triggering on non-standard muon signatures, such as those from LLP decays, at L1T.
Related
- Electromagnetic Shower Reconstruction and Identification in FASER's Emulsion Detector for LHC Forward Neutrino Measurements
- Reconstruction of Shower-like Events in NEON Using Likelihood and Graph Neural Network Methods
- Improving the CMS High Level Trigger tracking at the HL-LHC with novel and evolved heterogeneous algorithms
- Stable tracking of turbulence-disturbed laser communication spots using a time-series state fusion network
- SeriesXRD: automated reflection tracking and phase identification in high-pressure X-ray diffraction series
BibTeX
@misc{estrada2026fpgabased,
title = {{FPGA-based muon shower identification and graph neural network tracking algorithms for HL-LHC triggers}},
author = {Daniel Estrada and Elena Aller and Andrea Cardini and Santiago Folgueras and Pelayo Leguina and Javier Prado},
howpublished = {arXiv},
year = {2026},
month = oct,
doi = {10.48550/arxiv.2610.06379},
eprint = {2610.06379},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2610.06379},
}
RIS
TY - UNPB
TI - FPGA-based muon shower identification and graph neural network tracking algorithms for HL-LHC triggers
AU - Daniel Estrada
AU - Elena Aller
AU - Andrea Cardini
AU - Santiago Folgueras
AU - Pelayo Leguina
AU - Javier Prado
PY - 2026
DA - 2026/10/05
PB - arXiv
DO - 10.48550/arxiv.2610.06379
UR - https://arxiv.org/abs/2610.06379
AB - This work presents two hardware-accelerated strategies for the upgrade of the CMS Level-1 Trigger (L1T) to target efficiency losses due to highly energetic radiating muons and unconventional physics signatures, such as Long-Lived Particles (LLPs). Operating directly on low-level detector hits, the first strategy implements a dedicated muon shower identification algorithm in the CMS barrel region that monitors hit multiplicities in the Drift Tube chambers to generate Shower Primitives. Executing with sub-bunch-crossing latency and ultra-low resource consumption, this algorithm successfully tags showered muons and provides essential context for downstream track finders. The second approach targets the barrel-endcap transition (overlap) region by evaluating Graph Neural Networks to reconstruct displaced muon tracks. Following a divided methodology that first isolates hardware feasibility from evolving physics refinements, an initial proxy model based on a GraphSAGE architecture is evaluated to validate its viability on FPGAs within strict latency limits. This implementation utilizes an INT8-PO2 quantization technique coupled with a data-driven bit-width optimization. By replacing DSP-heavy fixed-point multiplications with fast compile-time arithmetic bit-shifts and allocating the minimum required bits per signal, this hardware-software co-design reduces DSP utilization to 20% and achieves a deterministic inference latency of just $19$ clock cycles. Together, these developments pave the way for triggering on non-standard muon signatures, such as those from LLP decays, at L1T.
ER -