A VLSI-Like Design and Verification Flow for Quantum Circuits: A Case Study in PI Estimation
Abstract
This paper proposes a VLSI-like design and verification flow for quantum circuit implementation, covering four levels: behavioral modeling, register-transfer level (RTL), gate level, and full-circuit integration with quantum algorithms. Using quantum Monte Carlo methods for pi estimation as a case study, the proposed flow provides a systematic path from initial specifications to large-scale quantum circuit implementation. The paper highlights two key contributions. First, quantum digital design supports a broad range of applications beyond predefined circuit templates. This capability is particularly important for application-specific operations in algorithms such as Shor's, Grover's, and quantum amplitude estimation (QAE), and can significantly advance fault-tolerant quantum computing (FTQC). Second, classical simulation shows that replacing random sampling with grid sampling can achieve a quadratic improvement in this pi-estimation case without quantum computation. This suggests that the quadratic speedup may arise from the grid sampling strategy rather than from the QAE circuit itself. By adapting conventional VLSI digital design principles, this four-level flow addresses a key bottleneck in quantum circuit design and enables flexible design initiation from multiple entry points, including specifications, RTL, and gate-level descriptions, paving the way for the practical deployment of quantum computing.
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BibTeX
@misc{kao2026vlsilike,
title = {{A VLSI-Like Design and Verification Flow for Quantum Circuits: A Case Study in PI Estimation}},
author = {Yu-Ting Kao and Yeong-Jar Chang},
howpublished = {arXiv},
year = {2026},
month = oct,
doi = {10.48550/arxiv.2610.39263},
eprint = {2610.39263},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2610.39263},
}
RIS
TY - UNPB
TI - A VLSI-Like Design and Verification Flow for Quantum Circuits: A Case Study in PI Estimation
AU - Yu-Ting Kao
AU - Yeong-Jar Chang
PY - 2026
DA - 2026/10/29
PB - arXiv
DO - 10.48550/arxiv.2610.39263
UR - https://arxiv.org/abs/2610.39263
AB - This paper proposes a VLSI-like design and verification flow for quantum circuit implementation, covering four levels: behavioral modeling, register-transfer level (RTL), gate level, and full-circuit integration with quantum algorithms. Using quantum Monte Carlo methods for pi estimation as a case study, the proposed flow provides a systematic path from initial specifications to large-scale quantum circuit implementation. The paper highlights two key contributions. First, quantum digital design supports a broad range of applications beyond predefined circuit templates. This capability is particularly important for application-specific operations in algorithms such as Shor's, Grover's, and quantum amplitude estimation (QAE), and can significantly advance fault-tolerant quantum computing (FTQC). Second, classical simulation shows that replacing random sampling with grid sampling can achieve a quadratic improvement in this pi-estimation case without quantum computation. This suggests that the quadratic speedup may arise from the grid sampling strategy rather than from the QAE circuit itself. By adapting conventional VLSI digital design principles, this four-level flow addresses a key bottleneck in quantum circuit design and enables flexible design initiation from multiple entry points, including specifications, RTL, and gate-level descriptions, paving the way for the practical deployment of quantum computing.
ER -