Statistical and Central Tendency Analyses of ESD-Induced Degradation in RF Circuits Using Combined ESD/DC/RF Measurements
Abstract
This work presents a comprehensive statistical analysis of electrostatic discharge (ESD) induced degradation in radio-frequency (RF) circuits using a combination of very fast transmission line pulse (vf-TLP), direct current (DC), and RF parameter measurements. This study focuses on a 10GHz low-noise amplifier (LNA) implemented in 28nm FD-SOI technology, where ultra fast ESD events with a rise time of 100ps and a pulse width of 1ns are applied at the circuit input. Unlike conventional approaches that rely solely on the DC supply current (IVdd) and the hard-failure leakage threshold as failure indicators, this work demonstrates that such criteria alone are insufficient to predict early-stage RF degradation, and identifies the gate-referenced bias current (Ibias) as a markedly more sensitive DC indicator that, once correlated with the RF figures of merit, enables the degradation onset to be located. A large population of devices is characterized before and after vf-TLP stress application, and statistical boxplot and central tendency analyses are performed on key RF parameters, including gain, noise figure, and input/output impedance matching. The results reveal that significant RF performance degradation occurs at stress levels 20%–25% below the conventional ESD failure threshold, depending on the RF parameter considered. Among the analyzed DC parameters, the bias current is identified as a highly sensitive indicator of oxide degradation and exhibits a strong correlation with RF performancedeterioration.Basedonthiscorrelation,anewRF-orientedpost-ESD circuit failure criterion is proposed using a 5% acceptable variation threshold, enabling early detection of functional degradation. This methodology provides an efficient alternative to extensive RF testing by enabling accurate prediction of RF reliability through combined ESD and DC measurements, thereby contributing to improved protection strategies and lifetime assessment of high-frequency integrated circuits.
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BibTeX
@article{guedes2026statistical,
title = {{Statistical and Central Tendency Analyses of ESD-Induced Degradation in RF Circuits Using Combined ESD/DC/RF Measurements}},
author = {Thalis da Costa Guedes and Jean-Marc Duchamp and Manuel Barragan and Loïc Vincent and Philippe Ferrari},
journal = {IEEE Access},
year = {2026},
month = aug,
doi = {10.1109/access.2026.3727918},
url = {https://hal.science/hal-05742631v1},
note = {CC BY-SA 4.0},
}
RIS
TY - JOUR
TI - Statistical and Central Tendency Analyses of ESD-Induced Degradation in RF Circuits Using Combined ESD/DC/RF Measurements
AU - Thalis da Costa Guedes
AU - Jean-Marc Duchamp
AU - Manuel Barragan
AU - Loïc Vincent
AU - Philippe Ferrari
PY - 2026
DA - 2026/08/28
JO - IEEE Access
DO - 10.1109/access.2026.3727918
UR - https://hal.science/hal-05742631v1
AB - This work presents a comprehensive statistical analysis of electrostatic discharge (ESD) induced degradation in radio-frequency (RF) circuits using a combination of very fast transmission line pulse (vf-TLP), direct current (DC), and RF parameter measurements. This study focuses on a 10GHz low-noise amplifier (LNA) implemented in 28nm FD-SOI technology, where ultra fast ESD events with a rise time of 100ps and a pulse width of 1ns are applied at the circuit input. Unlike conventional approaches that rely solely on the DC supply current (IVdd) and the hard-failure leakage threshold as failure indicators, this work demonstrates that such criteria alone are insufficient to predict early-stage RF degradation, and identifies the gate-referenced bias current (Ibias) as a markedly more sensitive DC indicator that, once correlated with the RF figures of merit, enables the degradation onset to be located. A large population of devices is characterized before and after vf-TLP stress application, and statistical boxplot and central tendency analyses are performed on key RF parameters, including gain, noise figure, and input/output impedance matching. The results reveal that significant RF performance degradation occurs at stress levels 20%–25% below the conventional ESD failure threshold, depending on the RF parameter considered. Among the analyzed DC parameters, the bias current is identified as a highly sensitive indicator of oxide degradation and exhibits a strong correlation with RF performancedeterioration.Basedonthiscorrelation,anewRF-orientedpost-ESD circuit failure criterion is proposed using a 5% acceptable variation threshold, enabling early detection of functional degradation. This methodology provides an efficient alternative to extensive RF testing by enabling accurate prediction of RF reliability through combined ESD and DC measurements, thereby contributing to improved protection strategies and lifetime assessment of high-frequency integrated circuits.
SN - 2169-3536
SN - 2169-3536
ER -