Fast Fault-Tolerant Decoders for Hypergraph Product and Lifted-Product Codes
Abstract
We design low-complexity, fault-tolerant decoders for quantum low-density parity-check (QLDPC) codes with the goal of reducing decoding latency. We target two major bottlenecks of decoding under the \emph{circuit-level} noise model: (i) post-processing via order-statistics decoding (OSD), and (ii) the large number of auxiliary variable nodes commonly introduced to represent CNOT-induced correlations during syndrome extraction. Our key observation is that propagating CNOT faults (\emph{hook errors}) create \emph{stabilizer-induced} trapping sets (TSs) that are intrinsic to hypergraph-product (HGP) and lifted-product (LP) constructions. Therefore, instead of modeling each such fault with an explicit correlation node and relying on OSD to clean up the resulting failures, we design message-passing decoders that resolve the corresponding \emph{stabilizer-induced} TSs directly. We obtain these decoders by deriving QLDPC decoders from decoders for the parent classical LDPC codes and using them collectively to correct broad families of \emph{stabilizer-induced} TSs. For CNOT faults that manifest primarily as syndrome errors, we show that their effect is equivalent to a data error together with syndrome-bit measurement errors. Consequently, given repeated measurements and a decoding graph that already includes nodes representing syndrome-bit errors, no distinct variable node is needed for each CNOT fault. Using a \emph{phenomenological} Tanner graph with nodes representing only data errors and syndrome-bit errors, simulations on LP codes show a significant improvement in logical error rate relative to BP+OSD. Moreover, the improved error correction relies on low-complexity finite-state iterative decoders, targeted for fast and low-latency FPGA implementation.
Related
- Graphical Analysis of Lifted Product Code Constructions
- Lifted-Product QLDPC Codes in the Polynomial Domain
- Coset Lifted Product Codes: Constructing Quantum LDPC Codes from Non-Normal Subgroup Actions
- Quasi-Static Fault-Tolerant Feedback Control of a Quadrotor under Rotor Failure with Provable Safety Guarantees
- Fault-Tolerant Nonlinear Control of Robotic Manipulator Using Neural Network
BibTeX
@misc{pradhan2026fast,
title = {{Fast Fault-Tolerant Decoders for Hypergraph Product and Lifted-Product Codes}},
author = {Asit Kumar Pradhan and Nithin Raveendran and David Declercq and Bane Vasić},
howpublished = {arXiv},
year = {2026},
month = oct,
doi = {10.48550/arxiv.2608.31040},
eprint = {2608.31040},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2608.31040},
}
RIS
TY - UNPB
TI - Fast Fault-Tolerant Decoders for Hypergraph Product and Lifted-Product Codes
AU - Asit Kumar Pradhan
AU - Nithin Raveendran
AU - David Declercq
AU - Bane Vasić
PY - 2026
DA - 2026/10/27
PB - arXiv
DO - 10.48550/arxiv.2608.31040
UR - https://arxiv.org/abs/2608.31040
AB - We design low-complexity, fault-tolerant decoders for quantum low-density parity-check (QLDPC) codes with the goal of reducing decoding latency. We target two major bottlenecks of decoding under the \emph{circuit-level} noise model: (i) post-processing via order-statistics decoding (OSD), and (ii) the large number of auxiliary variable nodes commonly introduced to represent CNOT-induced correlations during syndrome extraction. Our key observation is that propagating CNOT faults (\emph{hook errors}) create \emph{stabilizer-induced} trapping sets (TSs) that are intrinsic to hypergraph-product (HGP) and lifted-product (LP) constructions. Therefore, instead of modeling each such fault with an explicit correlation node and relying on OSD to clean up the resulting failures, we design message-passing decoders that resolve the corresponding \emph{stabilizer-induced} TSs directly. We obtain these decoders by deriving QLDPC decoders from decoders for the parent classical LDPC codes and using them collectively to correct broad families of \emph{stabilizer-induced} TSs. For CNOT faults that manifest primarily as syndrome errors, we show that their effect is equivalent to a data error together with syndrome-bit measurement errors. Consequently, given repeated measurements and a decoding graph that already includes nodes representing syndrome-bit errors, no distinct variable node is needed for each CNOT fault. Using a \emph{phenomenological} Tanner graph with nodes representing only data errors and syndrome-bit errors, simulations on LP codes show a significant improvement in logical error rate relative to BP+OSD. Moreover, the improved error correction relies on low-complexity finite-state iterative decoders, targeted for fast and low-latency FPGA implementation.
ER -