Characterization of a low-power 3D photon-to-digital converter readout improved for system integration in meter-scale applications
Abstract
Digital silicon photomultipliers (dSiPM) are arrays of single photon avalanche diodes (SPADs) where each SPAD has its own electronic readout. To maximize the photodetection area, we developed a readout integrated circuit (ROIC) 3D-integrated to a custom-designed SPAD layer fabricated at Teledyne Dalsa (Bromont, Canada) to form a photon-to-digital converter (PDC). This paper presents an improved version of a previously demonstrated ROIC, fabricated in TSMC 180 nm technology to manage a 64 x 64 pixel architecture. This ROIC has different outputs, such as a flag output that produces a pulse whenever one of the pixels triggers and a digital sum that samples the amount of triggered SPADs. Improvements lead to a reduction of the timing jitter on the flag output from 72.0 ps RMS to 22.6 ps RMS through optimized H-tree design. A tunable hold-off circuit provides adjustable dead time from 32 ns to 18 μs, addressing both afterpulsing mitigation and SPAD-to-SPAD variations due to process defects. Power consumption is lowered by 30% at trigger rates exceeding 10 kHz through digital logic optimization and clock gating. These measurements validated that the ROIC is ready for 3D integration into a PDC for systems in medical imaging, particle physics, and quantum sciences.
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BibTeX
@misc{lepage2026characterization,
title = {{Characterization of a low-power 3D photon-to-digital converter readout improved for system integration in meter-scale applications}},
author = {Olivier Lepage and Tommy Rossignol and Nicolas Roy and Gabriel Lessard and Frédéric Vachon and Lorenzo Fabris and Serge A. Charlebois and Jean-François Pratte},
howpublished = {arXiv},
year = {2026},
month = sep,
doi = {10.48550/arxiv.2609.01841},
eprint = {2609.01841},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2609.01841},
}
RIS
TY - UNPB
TI - Characterization of a low-power 3D photon-to-digital converter readout improved for system integration in meter-scale applications
AU - Olivier Lepage
AU - Tommy Rossignol
AU - Nicolas Roy
AU - Gabriel Lessard
AU - Frédéric Vachon
AU - Lorenzo Fabris
AU - Serge A. Charlebois
AU - Jean-François Pratte
PY - 2026
DA - 2026/09/01
PB - arXiv
DO - 10.48550/arxiv.2609.01841
UR - https://arxiv.org/abs/2609.01841
AB - Digital silicon photomultipliers (dSiPM) are arrays of single photon avalanche diodes (SPADs) where each SPAD has its own electronic readout. To maximize the photodetection area, we developed a readout integrated circuit (ROIC) 3D-integrated to a custom-designed SPAD layer fabricated at Teledyne Dalsa (Bromont, Canada) to form a photon-to-digital converter (PDC). This paper presents an improved version of a previously demonstrated ROIC, fabricated in TSMC 180 nm technology to manage a 64 x 64 pixel architecture. This ROIC has different outputs, such as a flag output that produces a pulse whenever one of the pixels triggers and a digital sum that samples the amount of triggered SPADs. Improvements lead to a reduction of the timing jitter on the flag output from 72.0 ps RMS to 22.6 ps RMS through optimized H-tree design. A tunable hold-off circuit provides adjustable dead time from 32 ns to 18 μs, addressing both afterpulsing mitigation and SPAD-to-SPAD variations due to process defects. Power consumption is lowered by 30% at trigger rates exceeding 10 kHz through digital logic optimization and clock gating. These measurements validated that the ROIC is ready for 3D integration into a PDC for systems in medical imaging, particle physics, and quantum sciences.
ER -