RISC-V-based YOLOv3-tiny acceleration with runtime-reconfigurable systolic arrays and custom instructions
- 1Tongda College, Nanjing University of Posts and Telecommunications
- 2School of Computer Science, Nanjing University of Posts and Telecommunications
- 3College of Information Engineering, Yangzhou Polytechnic Institute
Abstract
YOLOv3-tiny is widely used in edge-oriented object detection, but its deployment on resource-constrained platforms is limited by high computational cost and the limited flexibility of conventional processors. This paper presents a RISC-V-based acceleration framework for YOLOv3-tiny inference that combines a tightly coupled CPU-accelerator architecture with runtime-reconfigurable hardware support. A Hummingbird E203 core is integrated with a dedicated accelerator through the NICE interface, and 11 custom instructions are introduced for data movement, convolution control, and post-processing. The hardware adopts a runtime-reconfigurable systolic array supporting multiple convolution kernel sizes, together with activation, pooling, fully connected, and detection-oriented post-processing modules. The design is implemented on an Artix-7 FPGA and evaluated using a hardware-oriented YOLOv3-tiny workload, supplemented by module-level analysis and same-platform baseline comparisons. Experimental results show a 79.5% reduction in convolution execution time and a 4.89 × speed-up over the baseline RISC-V processor. Hardware-supported post-processing further reduces the cycle cost of sorting and IoU-related computation by 60.55% and 45.44%, respectively. These results demonstrate the effectiveness of the proposed processor-coupled acceleration architecture for YOLOv3-tiny-based detection inference on edge platforms.
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BibTeX
@article{wang2026riscvbased,
title = {{RISC-V-based YOLOv3-tiny acceleration with runtime-reconfigurable systolic arrays and custom instructions}},
author = {Shuya Wang and Xuecong Chen and Detao Nie and Fujun Wang},
journal = {Scientific Reports},
year = {2026},
month = jul,
doi = {10.1038/s41598-026-60759-5},
url = {https://doi.org/10.1038/s41598-026-60759-5},
note = {CC BY},
}
RIS
TY - JOUR
TI - RISC-V-based YOLOv3-tiny acceleration with runtime-reconfigurable systolic arrays and custom instructions
AU - Shuya Wang
AU - Xuecong Chen
AU - Detao Nie
AU - Fujun Wang
PY - 2026
DA - 2026/07/01
JO - Scientific Reports
DO - 10.1038/s41598-026-60759-5
UR - https://doi.org/10.1038/s41598-026-60759-5
AB - YOLOv3-tiny is widely used in edge-oriented object detection, but its deployment on resource-constrained platforms is limited by high computational cost and the limited flexibility of conventional processors. This paper presents a RISC-V-based acceleration framework for YOLOv3-tiny inference that combines a tightly coupled CPU-accelerator architecture with runtime-reconfigurable hardware support. A Hummingbird E203 core is integrated with a dedicated accelerator through the NICE interface, and 11 custom instructions are introduced for data movement, convolution control, and post-processing. The hardware adopts a runtime-reconfigurable systolic array supporting multiple convolution kernel sizes, together with activation, pooling, fully connected, and detection-oriented post-processing modules. The design is implemented on an Artix-7 FPGA and evaluated using a hardware-oriented YOLOv3-tiny workload, supplemented by module-level analysis and same-platform baseline comparisons. Experimental results show a 79.5% reduction in convolution execution time and a 4.89 × speed-up over the baseline RISC-V processor. Hardware-supported post-processing further reduces the cycle cost of sorting and IoU-related computation by 60.55% and 45.44%, respectively. These results demonstrate the effectiveness of the proposed processor-coupled acceleration architecture for YOLOv3-tiny-based detection inference on edge platforms.
SN - 2045-2322
ER -