PreprintCC BY 4.0Zenodo
Core Readout Hardware and Semiconductor Implementation Roadmap for the Decimal Photonic Continuous Computer
Abstract
This paper proposes a core optical readout hardware scheme for the decimal photonic continuous computer. Two oppositely oriented zero-bias weak PN junctions form a Twin Directional Settlement Cell, designed to convert optical directional responses into discrete digital states through independent material thresholds. Drawing on zero-bias tunnel detection, 1550 nm germanium photodetectors, and localized junction fabrication in two-dimensional semiconductors, the paper outlines an implementation pathway from dual-junction experimental verification to monolithic semiconductor integration. The proposed architecture provides a testable hardware approach for connecting continuous optical relational computation with discrete digital settlement.
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BibTeX
@misc{zhang2026core,
title = {{Core Readout Hardware and Semiconductor Implementation Roadmap for the Decimal Photonic Continuous Computer}},
author = {Xiangqian Zhang and Yuchuan Xu},
howpublished = {Zenodo},
year = {2026},
month = oct,
doi = {10.5281/zenodo.23470920},
url = {https://zenodo.org/records/23470920},
note = {CC BY 4.0},
}
RIS
TY - UNPB
TI - Core Readout Hardware and Semiconductor Implementation Roadmap for the Decimal Photonic Continuous Computer
AU - Xiangqian Zhang
AU - Yuchuan Xu
PY - 2026
DA - 2026/10/17
PB - Zenodo
DO - 10.5281/zenodo.23470920
UR - https://zenodo.org/records/23470920
AB - This paper proposes a core optical readout hardware scheme for the decimal photonic continuous computer. Two oppositely oriented zero-bias weak PN junctions form a Twin Directional Settlement Cell, designed to convert optical directional responses into discrete digital states through independent material thresholds. Drawing on zero-bias tunnel detection, 1550 nm germanium photodetectors, and localized junction fabrication in two-dimensional semiconductors, the paper outlines an implementation pathway from dual-junction experimental verification to monolithic semiconductor integration. The proposed architecture provides a testable hardware approach for connecting continuous optical relational computation with discrete digital settlement.
ER -