Time-Deterministic and Instruction-Dynamic Execution: A field-programmable gate array quantum-control processor
Abstract
Long-running quantum computations, including error-corrected workloads, demand instruction availability, measurement-dependent control, and calibration updates. We present Time-Deterministic and Instruction-Dynamic Execution, an FPGA quantum-control processor supporting runtime revision at both instruction and parameter levels. Dynamic Instruction Parameter Update supplies one-shot, next-match patches before parameter capture, while Dynamic Instruction Stream Overwrite provides guarded replacement, logical deletion, and out-of-line insertion in eligible future regions of a resident program. A moving fetch-visibility guard coordinates instruction updates with execution, and event commitment isolates complete descriptors for independent hardware-timed dispatch. Revision applicability depends on update timing and execution progress; deterministic service applies to committed events under the stated scheduling conditions. The Xilinx ZCU102 implementation uses a 250-MHz control core and a 425-MHz timing/update domain. FPGA-resident measurements at the registered digital interfaces confirmed programmed-cycle dispatch for all tested descriptors committed at least one timing-domain cycle before their timestamps, with downstream ready and the stated FIFO ordering conditions. Separate tests confirmed post-commit timestamp and payload invariance. The minimum all-success mapped DIPU margin was four control-domain cycles, and a replacement of L instruction words completed in L+5 update-domain cycles under continuous payload delivery. Within the tested guard-distance range, rejected DISO requests reported an error and preserved the resident path, whereas all admitted revisions tested here executed complete revised sequences. These results provide a hardware execution basis for incorporating runtime-generated sequences and parameter corrections into precisely timed quantum computations with feedback.
Versions
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BibTeX
@misc{luo2026timedeterministic,
title = {{Time-Deterministic and Instruction-Dynamic Execution: A field-programmable gate array quantum-control processor}},
author = {Xiaoqin Luo and Jiayun Song and Xiaolu Su},
howpublished = {arXiv},
year = {2026},
month = nov,
doi = {10.48550/arxiv.2608.15173},
eprint = {2608.15173},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2608.15173},
}
RIS
TY - UNPB
TI - Time-Deterministic and Instruction-Dynamic Execution: A field-programmable gate array quantum-control processor
AU - Xiaoqin Luo
AU - Jiayun Song
AU - Xiaolu Su
PY - 2026
DA - 2026/11/03
PB - arXiv
DO - 10.48550/arxiv.2608.15173
UR - https://arxiv.org/abs/2608.15173
AB - Long-running quantum computations, including error-corrected workloads, demand instruction availability, measurement-dependent control, and calibration updates. We present Time-Deterministic and Instruction-Dynamic Execution, an FPGA quantum-control processor supporting runtime revision at both instruction and parameter levels. Dynamic Instruction Parameter Update supplies one-shot, next-match patches before parameter capture, while Dynamic Instruction Stream Overwrite provides guarded replacement, logical deletion, and out-of-line insertion in eligible future regions of a resident program. A moving fetch-visibility guard coordinates instruction updates with execution, and event commitment isolates complete descriptors for independent hardware-timed dispatch. Revision applicability depends on update timing and execution progress; deterministic service applies to committed events under the stated scheduling conditions. The Xilinx ZCU102 implementation uses a 250-MHz control core and a 425-MHz timing/update domain. FPGA-resident measurements at the registered digital interfaces confirmed programmed-cycle dispatch for all tested descriptors committed at least one timing-domain cycle before their timestamps, with downstream ready and the stated FIFO ordering conditions. Separate tests confirmed post-commit timestamp and payload invariance. The minimum all-success mapped DIPU margin was four control-domain cycles, and a replacement of L instruction words completed in L+5 update-domain cycles under continuous payload delivery. Within the tested guard-distance range, rejected DISO requests reported an error and preserved the resident path, whereas all admitted revisions tested here executed complete revised sequences. These results provide a hardware execution basis for incorporating runtime-generated sequences and parameter corrections into precisely timed quantum computations with feedback.
ER -