Voltage-Increment-Based Low-Rank Representation with Polynomial Chaos Expansions for Probabilistic Voltage Assessment Under Multiple Contingencies
- 1State Key Laboratory of Power Transmission Equipment Technology, School of Electrical Engineering, Chongqing University, Chongqing 401331, China
- 2State Grid Gansu Electric Power Research Institute, Lanzhou 730070, China
Abstract
Probabilistic voltage assessment under multiple contingencies involves numerous network topologies and uncertain operating conditions, resulting in substantial surrogate modeling and computational costs. To address this problem, this paper proposes a voltage-increment-based low-rank (LR) representation with polynomial chaos expansion (PCE), denoted as LR-PCE-ΔV, for a unified multi-contingency voltage assessment. For each model-construction realization, the voltage increment ΔV is calculated as the difference between the post-contingency and pre-contingency bus voltages. The voltage increments under all contingencies are then stacked to form a joint multi-contingency voltage-increment response matrix. Singular value decomposition (SVD) is applied to extract the dominant modes, and one PCE surrogate is constructed for the coefficient of each retained mode. For a new input realization, the predicted modal coefficients are used to reconstruct the voltage increments under all contingencies, after which the corresponding pre-contingency voltages are added to recover the post-contingency voltages. The method is verified on the IEEE 118-bus system with 231 N − 1 contingencies against conventional Monte Carlo simulation (MCS), comprising the pre-contingency AC optimal power flow (ACOPF) and post-contingency AC power flow calculations (ACPF). The proposed method reduces the number of required PCE surrogates from 231 to 21. Compared with the corresponding low-rank model constructed directly from the post-contingency voltages, it reduces the RMSE by 85.9% and achieves a 7.7-fold speedup over conventional MCS while accurately reproducing voltage distributions.
Related
- Approximation and composition of functions in quantized tensor trains via orthogonal polynomial expansions
- Probabilistic representation and limit theorems for particle numbers of quasi-free states
- The Riesz representation in submetric spaces and its probabilistic aspects
- Probabilistic representation and Monte Carlo method for nonlinear Dirac equations
- Riordan array representation of recursive polynomial sequences, orthogonal polynomial sequences, and d-orthogonal polynomial sequences
BibTeX
@article{wang2026voltageincrementbased,
title = {{Voltage-Increment-Based Low-Rank Representation with Polynomial Chaos Expansions for Probabilistic Voltage Assessment Under Multiple Contingencies}},
author = {Yuzhi Wang and Xingyu Lin and Junzhou Wang and Liu Zhu and Chen Liang and Junjie Tang},
journal = {Mathematics},
year = {2026},
month = oct,
doi = {10.3390/math14193576},
url = {https://www.mdpi.com/2227-7390/14/19/3576},
note = {CC BY 4.0},
}
RIS
TY - JOUR
TI - Voltage-Increment-Based Low-Rank Representation with Polynomial Chaos Expansions for Probabilistic Voltage Assessment Under Multiple Contingencies
AU - Yuzhi Wang
AU - Xingyu Lin
AU - Junzhou Wang
AU - Liu Zhu
AU - Chen Liang
AU - Junjie Tang
PY - 2026
DA - 2026/10/02
JO - Mathematics
DO - 10.3390/math14193576
UR - https://www.mdpi.com/2227-7390/14/19/3576
AB - Probabilistic voltage assessment under multiple contingencies involves numerous network topologies and uncertain operating conditions, resulting in substantial surrogate modeling and computational costs. To address this problem, this paper proposes a voltage-increment-based low-rank (LR) representation with polynomial chaos expansion (PCE), denoted as LR-PCE-ΔV, for a unified multi-contingency voltage assessment. For each model-construction realization, the voltage increment ΔV is calculated as the difference between the post-contingency and pre-contingency bus voltages. The voltage increments under all contingencies are then stacked to form a joint multi-contingency voltage-increment response matrix. Singular value decomposition (SVD) is applied to extract the dominant modes, and one PCE surrogate is constructed for the coefficient of each retained mode. For a new input realization, the predicted modal coefficients are used to reconstruct the voltage increments under all contingencies, after which the corresponding pre-contingency voltages are added to recover the post-contingency voltages. The method is verified on the IEEE 118-bus system with 231 N − 1 contingencies against conventional Monte Carlo simulation (MCS), comprising the pre-contingency AC optimal power flow (ACOPF) and post-contingency AC power flow calculations (ACPF). The proposed method reduces the number of required PCE surrogates from 231 to 21. Compared with the corresponding low-rank model constructed directly from the post-contingency voltages, it reduces the RMSE by 85.9% and achieves a 7.7-fold speedup over conventional MCS while accurately reproducing voltage distributions.
SN - 2227-7390
ER -