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Real-Time Plasma State Prediction via FPGA-Accelerated Quantized Recurrent Probabilistic Neural Networks
Abstract
Real time plasma state estimation for control of Tokamak devices are challenging due to the stringent latency requirements of the plasma control system (PCS). We present an end-to-end workflow for deploying a recurrent probabilistic neural network (RPNN) on FPGA hardware. We combine architecture size reduction with quantization-aware training via QKeras. The model is then synthesized using hls4ml, targeting a Xilinx Alveo U50 device. We report a design that fits comfortably within all four resource budgets (DSP, LUT, FF, BRAM) at deterministic sub-10~μs single-timestep latency, meeting the requirements for real-time inference inside a model-predictive-control-style plasma control loop.
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BibTeX
@misc{gaytanvillarreal2026realtime,
title = {{Real-Time Plasma State Prediction via FPGA-Accelerated Quantized Recurrent Probabilistic Neural Networks}},
author = {Daniel Gaytan-Villarreal and Aiken Xie and Tu Pham and Rohit Sonker and Chiara Amendola and Matteo Cremonesi and Cong Hao and Jeff Schneider},
howpublished = {arXiv},
year = {2026},
month = sep,
doi = {10.48550/arxiv.2609.23141},
eprint = {2609.23141},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2609.23141},
}
RIS
TY - UNPB
TI - Real-Time Plasma State Prediction via FPGA-Accelerated Quantized Recurrent Probabilistic Neural Networks
AU - Daniel Gaytan-Villarreal
AU - Aiken Xie
AU - Tu Pham
AU - Rohit Sonker
AU - Chiara Amendola
AU - Matteo Cremonesi
AU - Cong Hao
AU - Jeff Schneider
PY - 2026
DA - 2026/09/19
PB - arXiv
DO - 10.48550/arxiv.2609.23141
UR - https://arxiv.org/abs/2609.23141
AB - Real time plasma state estimation for control of Tokamak devices are challenging due to the stringent latency requirements of the plasma control system (PCS). We present an end-to-end workflow for deploying a recurrent probabilistic neural network (RPNN) on FPGA hardware. We combine architecture size reduction with quantization-aware training via QKeras. The model is then synthesized using hls4ml, targeting a Xilinx Alveo U50 device. We report a design that fits comfortably within all four resource budgets (DSP, LUT, FF, BRAM) at deterministic sub-10~μs single-timestep latency, meeting the requirements for real-time inference inside a model-predictive-control-style plasma control loop.
ER -