Stitched surface codes: planar concatenation through GHZ corridors
Abstract
We present a fault-tolerant quantum-memory architecture that concatenates four distance-t rotated surface-code patches with the [[4,2,2]] outer code, encoding two logical qubits at code distance d = 2t in a physical footprint of N < 2(2t+1)^2 qubits on a square lattice with nearest-neighbor connectivity. The outer-code stabilizer generators XXXX and ZZZZ, each of physical weight 4t, are measured in situ via verified Greenberger-Horne-Zeilinger (GHZ) ancillae distributed through narrow corridors between adjacent patches, without lattice surgery or long-range gates. The outer-code gadgets introduce hyperedge fault mechanisms, but by design each decomposes into graphlike components, so the complete syndrome is decoded by a single minimum-weight-perfect-matching pass. Circuit-level simulations show logical error rates that scale as p^t, consistent with distance-2t protection. Finally, we implement the construction experimentally on a 105-qubit Willow superconducting processor in both the ZZ and XX memory bases. With the correlated-matching decoder, increasing the code distance from d = 4 to d = 6 reduces the block logical error rate by a factor of 1.52. The construction thus provides a near-term testbed for concatenated architectures beyond the standard surface code.
Related
- Surface plasmon-based detection for picosecond ultrasonics in planar gold-dielectric layer geometries
- PIN-PMN-PT Surface Planar Waveguides Realized via He⁺ Implantation.
- Exciton-Tunable Phase Control and Superstrong Coupling Through Multimode Polariton Engineering in Planar Waveguides
- Exploring Asymmetric QEC Code Concatenation
- Surface bubbles enhance evaporation through self-sustained thermocapillary vapor ejection
BibTeX
@misc{shalby2026stitched,
title = {{Stitched surface codes: planar concatenation through GHZ corridors}},
author = {Mohamed A. Shalby and Alexandre Bourassa and Amir Karamlou and Leigh Martin and Alexis Morvan and Nicholas Noll and Craig Gidney and Leonid P. Pryadko},
howpublished = {arXiv},
year = {2026},
month = oct,
doi = {10.48550/arxiv.2610.21357},
eprint = {2610.21357},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2610.21357},
}
RIS
TY - UNPB
TI - Stitched surface codes: planar concatenation through GHZ corridors
AU - Mohamed A. Shalby
AU - Alexandre Bourassa
AU - Amir Karamlou
AU - Leigh Martin
AU - Alexis Morvan
AU - Nicholas Noll
AU - Craig Gidney
AU - Leonid P. Pryadko
PY - 2026
DA - 2026/10/15
PB - arXiv
DO - 10.48550/arxiv.2610.21357
UR - https://arxiv.org/abs/2610.21357
AB - We present a fault-tolerant quantum-memory architecture that concatenates four distance-t rotated surface-code patches with the [[4,2,2]] outer code, encoding two logical qubits at code distance d = 2t in a physical footprint of N < 2(2t+1)^2 qubits on a square lattice with nearest-neighbor connectivity. The outer-code stabilizer generators XXXX and ZZZZ, each of physical weight 4t, are measured in situ via verified Greenberger-Horne-Zeilinger (GHZ) ancillae distributed through narrow corridors between adjacent patches, without lattice surgery or long-range gates. The outer-code gadgets introduce hyperedge fault mechanisms, but by design each decomposes into graphlike components, so the complete syndrome is decoded by a single minimum-weight-perfect-matching pass. Circuit-level simulations show logical error rates that scale as p^t, consistent with distance-2t protection. Finally, we implement the construction experimentally on a 105-qubit Willow superconducting processor in both the ZZ and XX memory bases. With the correlated-matching decoder, increasing the code distance from d = 4 to d = 6 reduces the block logical error rate by a factor of 1.52. The construction thus provides a near-term testbed for concatenated architectures beyond the standard surface code.
ER -