RSS-enabled hybrid-modulation 19-level switched-capacitor inverter with ninefold voltage boost inductorless soft-charging low device count and minimized LDP
- 1Department of Electrical Engineering, University of Mohaghegh Ardabili
Abstract
This paper proposes a single-source 19-level switched-capacitor inverter with a ninefold voltage gain for high-gain multilevel power conversion applications. The proposed topology employs 12 switches, six capacitors, and six diodes, and achieves high voltage boosting without using any inductive components. A key feature of the structure is the availability of inherent redundant switching states (RSS), which are exploited to provide additional capacitor charging paths and to minimize the longest discharging period (LDP). This reduces capacitor voltage ripple, mitigates the inrush charging current, and contributes to lower overall power losses. To generate the required switching signals, a hybrid pulse-width modulation (HPWM) strategy based on a combination of phase-shifted and level-shifted modulation techniques is developed. The proposed modulation scheme enables proper selection of redundant states while maintaining balanced capacitor voltages. In the proposed inverter, the maximum blocking voltage (MBV) is limited to 0.66Vmax for only four switches, whereas the remaining switches are subjected to 0.33Vmax or lower. Therefore, the voltage stress on semiconductor devices is effectively reduced, leading to lower device rating requirements and reduced implementation cost. The topology configuration, operating modes, capacitor self-balancing mechanism, HPWM strategy, capacitor sizing procedure, device current stress, and power-loss distribution are analyzed in detail. A comprehensive comparison with recently reported 17-level and 19-level switched-capacitor inverters shows that the proposed topology provides a favorable trade-off among voltage gain, component count, voltage stress, inductorless operation, and LDP reduction. Finally, a 710 W laboratory prototype is developed to verify the theoretical analysis. Experimental results confirm the generation of 19 output voltage levels, ninefold voltage boosting, stable capacitor voltage balancing, and reliable operation under rated conditions. The measured full-load efficiency reaches 96.8%, demonstrating the practical feasibility and high-performance capability of the proposed inverter.
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BibTeX
@article{mansourizadeh2026rssenabled,
title = {{RSS-enabled hybrid-modulation 19-level switched-capacitor inverter with ninefold voltage boost inductorless soft-charging low device count and minimized LDP}},
author = {Hossein Mansourizadeh and Majid Hosseinpour and Ali Seifi},
journal = {Scientific Reports},
year = {2026},
month = jul,
doi = {10.1038/s41598-026-64297-y},
url = {https://doi.org/10.1038/s41598-026-64297-y},
note = {CC BY},
}
RIS
TY - JOUR
TI - RSS-enabled hybrid-modulation 19-level switched-capacitor inverter with ninefold voltage boost inductorless soft-charging low device count and minimized LDP
AU - Hossein Mansourizadeh
AU - Majid Hosseinpour
AU - Ali Seifi
PY - 2026
DA - 2026/07/01
JO - Scientific Reports
DO - 10.1038/s41598-026-64297-y
UR - https://doi.org/10.1038/s41598-026-64297-y
AB - This paper proposes a single-source 19-level switched-capacitor inverter with a ninefold voltage gain for high-gain multilevel power conversion applications. The proposed topology employs 12 switches, six capacitors, and six diodes, and achieves high voltage boosting without using any inductive components. A key feature of the structure is the availability of inherent redundant switching states (RSS), which are exploited to provide additional capacitor charging paths and to minimize the longest discharging period (LDP). This reduces capacitor voltage ripple, mitigates the inrush charging current, and contributes to lower overall power losses. To generate the required switching signals, a hybrid pulse-width modulation (HPWM) strategy based on a combination of phase-shifted and level-shifted modulation techniques is developed. The proposed modulation scheme enables proper selection of redundant states while maintaining balanced capacitor voltages. In the proposed inverter, the maximum blocking voltage (MBV) is limited to 0.66Vmax for only four switches, whereas the remaining switches are subjected to 0.33Vmax or lower. Therefore, the voltage stress on semiconductor devices is effectively reduced, leading to lower device rating requirements and reduced implementation cost. The topology configuration, operating modes, capacitor self-balancing mechanism, HPWM strategy, capacitor sizing procedure, device current stress, and power-loss distribution are analyzed in detail. A comprehensive comparison with recently reported 17-level and 19-level switched-capacitor inverters shows that the proposed topology provides a favorable trade-off among voltage gain, component count, voltage stress, inductorless operation, and LDP reduction. Finally, a 710 W laboratory prototype is developed to verify the theoretical analysis. Experimental results confirm the generation of 19 output voltage levels, ninefold voltage boosting, stable capacitor voltage balancing, and reliable operation under rated conditions. The measured full-load efficiency reaches 96.8%, demonstrating the practical feasibility and high-performance capability of the proposed inverter.
SN - 2045-2322
ER -