Efficient Simulation of Gate Leakage Currents in Ultra-scaled Transistors from First Principles

Abstract

To ensure high electrostatic integrity in ultra-scaled field-effect transistors (FETs), thin gate dielectric layers are typically needed, potentially giving rise to (strong) leakage currents. Being able to model this effect is therefore crucial. Here, we show how gate leakage currents can be computed at the ab initio level in WS₂-hBN FETs by extending the well-established quantum transmitting boundary method (QTBM). Two main challenges are tackled: (i) the calculation of the open boundary conditions (OBCs) for the gate contacts and (ii) the solution of the resulting sparse linear system of equations A x = b where the matrix A possesses an unstructured sparsity pattern. We demonstrate that the proposed method outperforms the state of the art and can be readily applied to simulate transistors with gate lengths exceeding 25 nm.

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BibTeX RIS

BibTeX

@misc{dossena2026efficient,
  title = {{Efficient Simulation of Gate Leakage Currents in Ultra-scaled Transistors from First Principles}},
  author = {Mauro Dossena and Nicolas Vetsch and Alexander Maeder and Anders Winka and Vincent Maillou and Denghui Lu and Alexandros Nikolaos Ziogas and Jiang Cao and Mathieu Luisier},
  howpublished = {arXiv},
  year = {2026},
  month = oct,
  doi = {10.48550/arxiv.2610.40929},
  eprint = {2610.40929},
  archivePrefix = {arXiv},
  url = {https://arxiv.org/abs/2610.40929},
  note = {CC BY 4.0},
}

RIS

TY  - UNPB
TI  - Efficient Simulation of Gate Leakage Currents in Ultra-scaled Transistors from First Principles
AU  - Mauro Dossena
AU  - Nicolas Vetsch
AU  - Alexander Maeder
AU  - Anders Winka
AU  - Vincent Maillou
AU  - Denghui Lu
AU  - Alexandros Nikolaos Ziogas
AU  - Jiang Cao
AU  - Mathieu Luisier
PY  - 2026
DA  - 2026/10/29
PB  - arXiv
DO  - 10.48550/arxiv.2610.40929
UR  - https://arxiv.org/abs/2610.40929
AB  - To ensure high electrostatic integrity in ultra-scaled field-effect transistors (FETs), thin gate dielectric layers are typically needed, potentially giving rise to (strong) leakage currents. Being able to model this effect is therefore crucial. Here, we show how gate leakage currents can be computed at the ab initio level in WS_2-hBN FETs by extending the well-established quantum transmitting boundary method (QTBM). Two main challenges are tackled: (i) the calculation of the open boundary conditions (OBCs) for the gate contacts and (ii) the solution of the resulting sparse linear system of equations A x = b where the matrix A possesses an unstructured sparsity pattern. We demonstrate that the proposed method outperforms the state of the art and can be readily applied to simulate transistors with gate lengths exceeding 25 nm.
ER  -

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