Ta-based S-I-S junctions for integrated superconducting Electronics
Abstract
In this work, we have presented S-I-S Josephson junctions with α-Ta electrodes and a TaOx barrier. We grew base and top α-Ta electrodes using seed layer engineering, showing both Nb and TaNx are viable seed layer choices, and particularly emphasize that at room temperature a re-seed layer is required to nucleate α-Ta for the top electrode. However, we note that the choice of seed layer can have subtle implications on the electrical tunneling behavior of the junctions. We used room-temperature probing of variable junction areas, combined with Ambegaokar-Baratoff physics, to characterize the wafer scale critical current densities. For 0.4 μm2 junctions, we found junction spreads as low as 2.0% across the 20 x 20 mm chip relevant for device performance. The entire process was carried out using standard industry foundry processing using 150 mm wafer tooling, which is an important step towards proving that Ta-based junctions can be implemented at scale. We have successfully fabricated and tested junctions with α-Ta electrodes and a TaOx insulating tunnel barrier, demonstrating that this is a material platform which merits further investigation and studies for potential application in classical and quantum superconducting technologies.
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BibTeX
@misc{borman2026tabased,
title = {{Ta-based S-I-S junctions for integrated superconducting Electronics}},
author = {Trent Borman and Cameron Bullock and Cole Chason and Bradley Christensen and Jonathan Cochran and Emad Din and Evan Donohue and Jason Flagg and A. L. Graninger and Eric Jones and Robert Klaes and Shawn Keebaugh and Erin Kennedy and John Kula and Jason Lapano and Melissa Loving and Christopher Pasco and Devika Pathan and Tam Pham and Timothy Pillsbury and Robert Pownall and Paige Quarterman and Jacob Ruf and Jade Simmons and Nathan Siwak and Joel Strand and Yong Mo Yang},
howpublished = {arXiv},
year = {2026},
month = nov,
doi = {10.48550/arxiv.2611.04982},
eprint = {2611.04982},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2611.04982},
}
RIS
TY - UNPB
TI - Ta-based S-I-S junctions for integrated superconducting Electronics
AU - Trent Borman
AU - Cameron Bullock
AU - Cole Chason
AU - Bradley Christensen
AU - Jonathan Cochran
AU - Emad Din
AU - Evan Donohue
AU - Jason Flagg
AU - A. L. Graninger
AU - Eric Jones
AU - Robert Klaes
AU - Shawn Keebaugh
AU - Erin Kennedy
AU - John Kula
AU - Jason Lapano
AU - Melissa Loving
AU - Christopher Pasco
AU - Devika Pathan
AU - Tam Pham
AU - Timothy Pillsbury
AU - Robert Pownall
AU - Paige Quarterman
AU - Jacob Ruf
AU - Jade Simmons
AU - Nathan Siwak
AU - Joel Strand
AU - Yong Mo Yang
PY - 2026
DA - 2026/11/03
PB - arXiv
DO - 10.48550/arxiv.2611.04982
UR - https://arxiv.org/abs/2611.04982
AB - In this work, we have presented S-I-S Josephson junctions with α-Ta electrodes and a TaO_x barrier. We grew base and top α-Ta electrodes using seed layer engineering, showing both Nb and TaN_x are viable seed layer choices, and particularly emphasize that at room temperature a re-seed layer is required to nucleate α-Ta for the top electrode. However, we note that the choice of seed layer can have subtle implications on the electrical tunneling behavior of the junctions. We used room-temperature probing of variable junction areas, combined with Ambegaokar-Baratoff physics, to characterize the wafer scale critical current densities. For 0.4 μm^2 junctions, we found junction spreads as low as 2.0% across the 20 x 20 mm chip relevant for device performance. The entire process was carried out using standard industry foundry processing using 150 mm wafer tooling, which is an important step towards proving that Ta-based junctions can be implemented at scale. We have successfully fabricated and tested junctions with α-Ta electrodes and a TaO_x insulating tunnel barrier, demonstrating that this is a material platform which merits further investigation and studies for potential application in classical and quantum superconducting technologies.
ER -