Fault-tolerant and fully addressable unitary logical gates via round-robin sparsification
Abstract
For quantum low-density parity check (qLDPC) codes, the ability to manipulate individual logical units of information, i.e. the use of addressable gates, enables maximal utility of their efficient encoding. We introduce explicit low-depth unitary circuits that realize fully addressable and fault-tolerant two-qubit Clifford gates for a subset of two-dimensional translationally invariant qLDPC codes. Our transversal unitaries are created by applying a geometrically structured sparsification procedure to round-robin circuits. We verify the general applicability of our protocol by proposing and numerically simulating a range of addressable CZs between toric, cyclic hypergraph-product, color, gross, and directional codes, demonstrating fault-tolerant memory-like logical error rate scaling.
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BibTeX
@misc{sahay2026faulttolerant,
title = {{Fault-tolerant and fully addressable unitary logical gates via round-robin sparsification}},
author = {Kaavya Sahay and Cody Jones},
howpublished = {arXiv},
year = {2026},
month = oct,
doi = {10.48550/arxiv.2610.03594},
eprint = {2610.03594},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2610.03594},
}
RIS
TY - UNPB
TI - Fault-tolerant and fully addressable unitary logical gates via round-robin sparsification
AU - Kaavya Sahay
AU - Cody Jones
PY - 2026
DA - 2026/10/02
PB - arXiv
DO - 10.48550/arxiv.2610.03594
UR - https://arxiv.org/abs/2610.03594
AB - For quantum low-density parity check (qLDPC) codes, the ability to manipulate individual logical units of information, i.e. the use of addressable gates, enables maximal utility of their efficient encoding. We introduce explicit low-depth unitary circuits that realize fully addressable and fault-tolerant two-qubit Clifford gates for a subset of two-dimensional translationally invariant qLDPC codes. Our transversal unitaries are created by applying a geometrically structured sparsification procedure to round-robin circuits. We verify the general applicability of our protocol by proposing and numerically simulating a range of addressable CZs between toric, cyclic hypergraph-product, color, gross, and directional codes, demonstrating fault-tolerant memory-like logical error rate scaling.
ER -