Topology-aware HVT MTCMOS power gating for power–delay optimization of cascaded transmission-gate MUX and DEMUX
- 1Department of Electrical, Electronic and Communication Engineering, Military Institute of Science and Technology (MIST)
Abstract
Multiplexers (MUXs) and demultiplexers (DEMUXs) are essential data-routing circuits used in memory addressing, processor datapaths, communication interfaces, and reconfigurable systems. However, CMOS scaling increases leakage power, while conventional MTCMOS techniques introduce delay, series-resistance, and control overhead. This work proposes a topology-aware high-threshold-voltage (HVT) MTCMOS power-gating architecture for cascaded transmission-gate (TG) based 4:1 MUX and 1:4 DEMUX circuits in 90 nm CMOS. The architecture uses a select-controlled HVT PMOS header at a topology-dependent TG stage and a block-level HVT header, requiring only two additional transistors without a dedicated sleep network. The MUX reduces power by 40.0% with a 16.0% delay penalty and improves PDP by 30.4%. The DEMUX reduces power by 28.6% and delay by 57.2%, achieving 69.4% lower PDP and 86.9% lower EDP. RC-delay analysis explains the topology-dependent behavior and establishes a scalable stage-selection principle. Cadence Virtuoso simulations, PVT analysis, Monte Carlo analysis, and DC sweeps confirm circuit robustness and functional integrity.
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BibTeX
@article{kabbo2026topologyaware,
title = {{Topology-aware HVT MTCMOS power gating for power–delay optimization of cascaded transmission-gate MUX and DEMUX}},
author = {Mahfuzur Rahman Kabbo and Md. Tawfiq Amin},
journal = {Discover Electronics},
year = {2026},
month = oct,
doi = {10.1007/s44291-026-00304-w},
url = {https://doi.org/10.1007/s44291-026-00304-w},
note = {CC BY},
}
RIS
TY - JOUR
TI - Topology-aware HVT MTCMOS power gating for power–delay optimization of cascaded transmission-gate MUX and DEMUX
AU - Mahfuzur Rahman Kabbo
AU - Md. Tawfiq Amin
PY - 2026
DA - 2026/10/25
JO - Discover Electronics
DO - 10.1007/s44291-026-00304-w
UR - https://doi.org/10.1007/s44291-026-00304-w
AB - Multiplexers (MUXs) and demultiplexers (DEMUXs) are essential data-routing circuits used in memory addressing, processor datapaths, communication interfaces, and reconfigurable systems. However, CMOS scaling increases leakage power, while conventional MTCMOS techniques introduce delay, series-resistance, and control overhead. This work proposes a topology-aware high-threshold-voltage (HVT) MTCMOS power-gating architecture for cascaded transmission-gate (TG) based 4:1 MUX and 1:4 DEMUX circuits in 90 nm CMOS. The architecture uses a select-controlled HVT PMOS header at a topology-dependent TG stage and a block-level HVT header, requiring only two additional transistors without a dedicated sleep network. The MUX reduces power by 40.0% with a 16.0% delay penalty and improves PDP by 30.4%. The DEMUX reduces power by 28.6% and delay by 57.2%, achieving 69.4% lower PDP and 86.9% lower EDP. RC-delay analysis explains the topology-dependent behavior and establishes a scalable stage-selection principle. Cadence Virtuoso simulations, PVT analysis, Monte Carlo analysis, and DC sweeps confirm circuit robustness and functional integrity.
SN - 2948-1600
ER -