Experimental validation of a compact fault-tolerant architecture for trapped ions
Abstract
Quantum error correction (QEC) is beginning to enable logical operations that outperform their unencoded physical counterparts, but useful fault-tolerant computation will require more than low-error quantum memory. An effective architecture must orchestrate efficient logical encoding, low-overhead logical operations, and access to the non-Clifford resources required for universal computation. Here, we introduce and experimentally validate such an architecture based on the $[[20,2,6]]$ C4-Helix code, designed for the early fault-tolerant regime. Using Quantinuum Helios, a 98-qubit trapped-ion quantum processor, we experimentally demonstrate the principal components of this architecture: we perform repeated quantum error correction with an error of 4.6+6.2−2.6×10−5 per logical qubit per QEC cycle. We benchmark the complete Clifford group on the two logical qubits of a single codeblock under active error correction, obtaining an error of 2.8+1.0−1.6× 10−4 per two-qubit logical Clifford. We further demonstrate a fault-tolerant chain-map interface between C4-Helix and a distance-5 surface code, preparing a heterogeneous three-logical-qubit GHZ state with a fidelity lower bound of 99.925+0.068−0.245%. In each case, the encoded implementation outperforms its corresponding unencoded physical baseline without relying on postselection. Circuit-level simulations indicate that improvements in physical fidelity bring the same architecture into the 10−6-10−8 logical-error regime targeted for early fault-tolerant computation. Together, these results establish C4-Helix as a hardware-validated fault-tolerant architecture rather than a bare quantum memory.
Related
- Below-threshold execution of fault-tolerant ripple-carry addition on a trapped-ion quantum computer
- Computing 256-bit elliptic curve discrete logarithms in 26 days on a fault-tolerant trapped-ion quantum computer with 20,000 qubits
- Encodings and Node Architecture: Lessons from the Fault-Tolerant Distributed Transversal Fanout
- Design and Finite-Element Analysis of a New Inclined Blade-Electrode Architecture for Trapped-Ion Quantum Information Processing
- Loss-correcting fault-tolerant quantum computing architecture for neutral atoms
BibTeX
@misc{berthusen2026experimental,
title = {{Experimental validation of a compact fault-tolerant architecture for trapped ions}},
author = {Noah Berthusen and Ali Lavasani and Asmae Benhemou and M. S. Allman and Joan Dreiling and Brian Estey and Cameron Foltz and Trent Jacobs and Michael Mills and Annie Jihyun Park and Adam P. Reed and David Hayes and Tzvetan S. Metodi and Andrew C. Potter},
howpublished = {arXiv},
year = {2026},
month = sep,
doi = {10.48550/arxiv.2609.03194},
eprint = {2609.03194},
archivePrefix = {arXiv},
url = {https://arxiv.org/abs/2609.03194},
note = {CC BY 4.0},
}
RIS
TY - UNPB
TI - Experimental validation of a compact fault-tolerant architecture for trapped ions
AU - Noah Berthusen
AU - Ali Lavasani
AU - Asmae Benhemou
AU - M. S. Allman
AU - Joan Dreiling
AU - Brian Estey
AU - Cameron Foltz
AU - Trent Jacobs
AU - Michael Mills
AU - Annie Jihyun Park
AU - Adam P. Reed
AU - David Hayes
AU - Tzvetan S. Metodi
AU - Andrew C. Potter
PY - 2026
DA - 2026/09/02
PB - arXiv
DO - 10.48550/arxiv.2609.03194
UR - https://arxiv.org/abs/2609.03194
AB - Quantum error correction (QEC) is beginning to enable logical operations that outperform their unencoded physical counterparts, but useful fault-tolerant computation will require more than low-error quantum memory. An effective architecture must orchestrate efficient logical encoding, low-overhead logical operations, and access to the non-Clifford resources required for universal computation. Here, we introduce and experimentally validate such an architecture based on the $[[20,2,6]]$ C_4-Helix code, designed for the early fault-tolerant regime. Using Quantinuum Helios, a 98-qubit trapped-ion quantum processor, we experimentally demonstrate the principal components of this architecture: we perform repeated quantum error correction with an error of 4.6^+6.2_−2.6×10^−5 per logical qubit per QEC cycle. We benchmark the complete Clifford group on the two logical qubits of a single codeblock under active error correction, obtaining an error of 2.8^+1.0_−1.6× 10^−4 per two-qubit logical Clifford. We further demonstrate a fault-tolerant chain-map interface between C_4-Helix and a distance-5 surface code, preparing a heterogeneous three-logical-qubit GHZ state with a fidelity lower bound of 99.925^+0.068_−0.245%. In each case, the encoded implementation outperforms its corresponding unencoded physical baseline without relying on postselection. Circuit-level simulations indicate that improvements in physical fidelity bring the same architecture into the 10^−6-10^−8 logical-error regime targeted for early fault-tolerant computation. Together, these results establish C_4-Helix as a hardware-validated fault-tolerant architecture rather than a bare quantum memory.
ER -